DS89C420-QCL Datasheet, PDF (32/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
ROM Size Select (ROMSIZE)
7
6
5
4
3
SFR C2h
—
—
—
—
PRAME
R-1
R-1
R-1
R-1
RT-0
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset
Bits 7–4
These bits are reserved. Read data is 1.
2
RMS2
RT-1
1
RMS1
RT-0
0
RMS0
RT-1
PRAME
Bit 3
Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program
space between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed
to this 1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX
data space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When
clear (= 0), the internal 1k RAM is not accessible as program space.
RMS2–0
Bits 2–0
ROM Memory Size Select 2-0. This register is used to select the maximum on-chip decoded
address. Care must be taken that the memory location of the current program counter is valid
both before and after modification. These bits can only be modified using a timed-access procedure.
The EA pin overrides the function of these bits when asserted, forcing the device to access external
program memory only. Configuring this register to a setting that exceeds the maximum amount of
internal memory can corrupt device operation. These bits default on reset to the maximum amount
of internal program memory (i.e., 16k for DS89C420).
On-Chip ROM Address
.
RS2 RS1
RS0 MAXIMUM ON-CHIP ROM ADDRESS
0
0
0 0kB/Disable on-chip ROM
0
0
1 1kB/03FFh
0
1
0 2kB/07FFh
0
1
1 4kB/0FFFh
1
0
0 8kB/1FFFh
1
0
1 16kB/3FFFh (DS89C420/430 default)
1
1
0 32kB/7FFFh (DS89C440 default)
1
1
1 64kB/FFFFh (DS89C450 default)
Power Management Register (PMR)
7
6
5
4
SFR C4h
CD1
CD0
SWB
CTM
RW*-1
RW*-0
RW-0
RW*-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
3
4X / 2X
RW*-0
2
ALEON
RW-0
1
DME1
RW-0
0
DME0
RW-0
CD1, CD0
Bits 7, 6
Clock Divide Control 1-0. These bits select the number of crystal oscillator clocks required to
generate one machine cycle. Switching between modes requires a transition through the default
divide-by-1 mode (CD1, CD0 = 10b). Attempts to perform an invalid transition are ignored. For
example, going from the crystal multiplier 2X mode to the divide-by-1024 mode would require first
switching from the 2X crystal multiplier mode to the divide-by-1 mode, followed by the switch from
the divide-by-1 to the divide-by-1024 mode. These bits cannot be modified when running from the
internal ring oscillator (RGMD = 1). The divide-by-1024 setting (CD1,CD0 = 11b) cannot be selected
when switchback is enabled (SWB = 1) and a switchback source (serial port or external interrupt)
is active.
CD1,
CD0
00
01
10
11
CLOCK FUNCTION
Crystal multiplier (4X or 2X mode as determined by PMR.3)
Reserved (forced into divide-by-1 mode if set)
Divide-by-1 (default state)
Divide-by-1024
The setting of these bits affects timer and serial port operation. Tables located in the SFR decription
for CKCON (8Eh) detail the respective operational dependencies on these bits.
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