DS89C420-QCL Datasheet, PDF (52/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 00b (ONE CYCLE) (CONTINUED)
The first diagram below illustrates the JBC bit, rel (3 bytes, four cycles) instruction for the case where the tested bit is clear and the
jump is not taken. Note that one stall cycle must be inserted since the cycle count exceeds the byte count by one. The RET (1 byte,
three cycles) instruction that follows requires insertion of two stall cycles. In this example, the return address is on a different 256-byte
page than the RET instruction, thus resulting in a page-miss memory cycle. The MOV direct, #data (3 bytes, three cycles) executed
next provides an example of an instruction not requiring any stall cycles.
The second diagram shows the same JBC bit, rel instruction for the case where the tested bit is set and the jump is taken. Since the
bit must be cleared and involves one of the special registers (PSW, SP, DPS, IE, EIE, IP0, IP1, EIP0, EIP1), a fifth memory cycle is
required. For this example, the jump taken by the JBC instruction crosses a 256-byte page boundary, while the RET instruction stays
on the same page.
1-CYCLE PAGE MODE 1: (PAGE MISS) – JBC bit, rel (4 CYCLES) – RET – (PAGE MISS) – MOV direct, data
SYSCLK
ALE
PSEN
PORT2
MISS
HIT HIT stall HIT stall stall
LSB
LSB
MISS
HIT HIT HIT HIT _HIT HIT
PORT0
10 ^{D1 1D}
22
JBC PSW.1, $+20h
RET
75 90 ⁵⁵
MOV P1,#55h
1-CYCLE PAGE MODE 1: (PAGE MISS) – JBC bit, rel (5 CYCLES) – (PAGE MISS) -- RET – MOV direct, data
SYSCLK
ALE
PSEN
PORT2
PORT0
MISS
HIT HIT stall stall
LSB
MISS
stall stall HIT HIT _HIT HIT HIT HIT
10 ^{D1 1D}
22
75 90 55
JBC PSW.1, $+20h
RET
MOV P1,#55h
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