DS89C420-QCL Datasheet, PDF (61/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Table 6-2. Data Memory Access Control
DME1
0
X
1
DME0
0
1
0
DATA MEMORY ADDRESS RANGE
0000h–FFFFh
0000h–03FFh
Reserved
DATA MEMORY LOCATION
External Data Memory (default)
Internal Data Memory
E _RleDserveMd
When configured as program memory, code fetches and MOVC read operations can be directed to this 1kB internal SRAM. To enable
the 1kB SRAM as internal program memory, software must set the PRAME bit (ROMSIZE.3). After setting this bit, code accesses to the
address range 0400h–07FFh are made to the internal 1kB SRAM in place of the program memory previously mapped to that address
range. For applications using only external program memory (EA = 0), the internal 1kB SRAM cannot be enabled as program space.
The internal 1kB SRAM can serve as merged program/data memory if both the DME0 and PRAME bits have been set. This feature can
be effective for changing small pieces of frequently executed code, but be cautious when employing self-modifying code techniques.
PROGRAM MEMORY INTERFACE—NONPAGE MODE
The ultra-high-speed flash microcontroller defaults to a nonpage mode, external program memory interface. This memory interconnect
scheme is the same as is used for the high-speed microcontroller family, and is shown in Figure 6-2. This example uses the DS89C420
and one 64k x 8 memory device. The program store enable (PSEN) signal is used to provide an output enable to the memory. It can
also be used to provide a chip enable, but this generally results in less-favorable timing. The address LSB and data are multiplexed
on port 0, and the address MSB is provided on port 2. An external latch, shown in the diagram as a 74F373, is used to latch the lower
byte of the address to the memory device. The address latch enable (ALE) signal controls the timing of the latch so that the operation
is performed in the proper sequence. The signals and relative timing for a program access are shown in Figure 6-3.
When implementing a high-speed memory interface, the F series (or faster) logic should be used. HC logic has worst-case propaga-
tion delays that are too long. Specifications for all devices should be checked. More information on the nonpage mode memory inter-
face timing can be found in Application Note 57 (DS80C320 Memory Interface Timing) and Application Note 85 (High-Speed
Microcontroller Interface Timing).
The DS89C420 provides an extremely high-speed interface to external memory. This allows for use of the slowest, and least expen-
sive, memory device for a given crystal speed. The ultra-high-speed flash microcontroller provides very fast slew rates to allow the
maximum possible time for memory access. Refer to the electrical specifications for exact timing.
Figure 6-3 shows the timing relationship for internal and external nonpage mode code fetches when CD1:0 = 10b. Note that an exter-
nal program fetch takes four system clocks, and an internal program fetch requires only one system clock.
PSEN
ALE
PORT 0
DS89C4x0
CK
74F373
LATCH
LSB ADDRESS ₍₈₎
DATA BUS
(8)
OE
64kB X 8
MEMORY
CE
PORT 2
MSB ADDRESS (7)
Figure 6-2. Program Memory Interconnect (Nonpage Mode)
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