DS89C420-QCL Datasheet, PDF (64/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
During a page miss, P2 drives the Addr [15:8] of the 16-bit address and holds it for the duration of the first half of the memory cycle
to allow the external address latches to latch the new most significant address byte. ALE is asserted to strobe the external address
latches. During this operation, PSEN, RD, and WR are all held in inactive states and P0 is in a high-impedance state. The following half-
memory cycle is executed as a page-hit cycle and the appropriate operation takes place.
A page-miss can occur at set intervals or during external operations that require a memory access into a page of memory that has not
been accessed during the last external cycle. Generally, the first external memory access causes a page miss. The new page address
is stored internally and is used to detect a page miss for the current external memory cycle.
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:
• PSEN is asserted for both page hit and page miss for a full clock cycle.
• The execution of external MOVX instruction causes a page miss.
• A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction.
The figure below shows external memory cycles for the page mode 1 bus structure. The first case illustrates a back-to-back MOVX
execution sequence for one-cycle page mode (PAGES 1:0 = 00b). PSEN remains active during page-hit cycles, and page misses are
forced during and after MOVX executions, independent of the most significant byte of the subsequent addresses. The second case
illustrates a MOVX execution sequence for two-cycle page mode (PAGES 1:0 = 01b). PSEN is active for a full clock cycle in code fetch-
es. Note that the page misses in this sequence are caused by changing of the most significant byte of the data address. The third case
illustrates a MOVX execution sequence for four-cycle page mode (PAGES 1:0 = 10b). There is no page-miss in this execution cycle,
as the most significant byte of the data address is assumed to match the last program address.
Internal Memory Cycles
XTAL1
ALE
PSEN
RD / WR
Port 0
External Memory Cycles
Inst Inst MOVX MOVX
Data
Inst
Data
PAGES=00
Port 2
ALE
PSEN
RD / WR
Port 0
Port 2
ALE
PSEN
RD / WR
Port 0
Port 2
MSB LSB
Page Miss
LSB LSB LSB MSB LSB
Page Hit
Data Access
MOVX executed
MSB LSB MSB LSB MSB
Page Miss
Data Access
MOVX executed
MOVX
Inst
Data
MSBAdd
LSB Add
Page Miss
LSB Add
MSBAdd
LSB Add
Page Hit
Data Access
MOVX executed
MSBAdd
Page Miss
next instruction
PAGES=01
MSBAdd
Page Miss
Inst
LSB Add
Data
LSB Add
Data Access
PAGES=10
Figure 6-5. Page Mode 1 External Memory Cycle (CD1:0 = 10b)
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