DS89C420-QCL Datasheet, PDF (13/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PSW.6
Auxiliary Carry
AC
Set when the previous operation resulted in a carry (during addition) or a borrow (during
subtraction) from the high-order nibble. Otherwise cleared.
PSW.2
Overflow
OV
For addition, OV is set when a carry is generated into a high order bit (bit 6 or bit 7), but not a carry
out of the same high-order bit. For subtraction, OV is set if a borrow is needed into a high order bit
(bit 6 or bit 7), but not into the other high-order bit. For multiplication, OV is set when the product
exceeds FFh. For division, OV is always cleared.
PSW.0
Parity
P
Set to logic 1 to indicate an odd number of ones in the accumulator (odd parity). Cleared for an
even number of ones. This produces even parity.
*All of these bits are cleared to a logic 0 for all resets.
Table 4-1. Instructions that Affect Flag Settings
INSTRUCTION
FLAGS
INSTRUCTION
C
OV
AC
ADD
X
X
X
CLR C
ADDC
X
X
X
CPL C
SUBB
X
X
X
ANL C, bit
MUL
0
X
ANL C, bit
DIV
0
X
ORL C, bit
DA
X
ORL C, bit
RRC
X
MOV C, bit
RLC
X
CJNE
SETB C
1
—
Note: X indicates the modification is according to the result of the instruction.
FLAGS
C
OV
AC
0
X
X
X
X
X
X
X
—
SPECIAL-FUNCTION REGISTER LOCATIONS
The ultra-high-speed flash microcontroller, like the 8051, uses SFRs to control peripherals and modes. In many cases, an SFR controls
individual functions or report status on individual functions. The SFRs reside in register locations 80h–FFh and are reached using direct
addressing. SFRs that end in 0 or 8 are bit addressable.
All standard SFR locations from the original 8051 are duplicated, with several additions. Tables are provided to illustrate the locations
of the SFRs and the default reset conditions of all SFR bits. Detailed descriptions of each SFR follow.
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