DS89C420-QCL Datasheet, PDF (72/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 DATA MEMORY TIMING–PAGES 1:0 = 01b (TWO CYCLES)
The first diagram below shows execution of back-to-back MOVX instructions from internal flash memory. A stretch value = 0 (MD2:0 =
000b) has been assigned. Note that the internal memory cycles consist of one system clock while the external memory cycles consist
of two system clocks (page hit) or four system clocks (page miss).
The second diagram below illustrates the timing of the MOVX operation with stretch value = 1 (MD2:0 = 001b). The stretch cycle (four
system clocks) is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR
pulse duration, and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is
added to the duration of the RD or WR pulse.
2-CYCLE PAGE MODE 1: MOVX (2 CYCLE) — MOVX (2 CYCLES)
SYSCLK
ALE
PSEN
WR / _RD
PORT2
MOVX #1
MSB
MOVX #1
LSB
PORT0
MOVX MOVX
#1 #2
MOVX
DATA
MOVX #1
Data Access
(Page Miss)
INST
2-CYCLE PAGE MODE 1: MOVX (3 CYCLES)
MOVX #2
MSB
MOVX #2
LSB
MOVX
DATA
MOVX #2
Data Access
(Page Miss)
INSTRUCTIONS
SYSCLK
ALE
PSEN
WR / _RD
PORT2
PORT0
MOVX MSB
MOVX LSB
MOVX DATA
MOVX INST
MOVX
Data Access
(Page Miss + 1 Stretch Cycle)
INSTRUCTIONS
= STRETCH CYCLE
_____________________________________________________________________________________________ 72