DS89C420-QCL Datasheet, PDF (48/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 10b (FOUR CYCLES)
(CONTINUED)
The first diagram below shows execution of the INC direct instruction (2 byte, two or three cycles) for the cases where an extra memory cycle is not
(INC DPL) and is (INC DPS) required.
The second diagram illustrates execution of the ACALL instruction whose destination address is on a different 256-byte page. Therefore, the second
execution cycle of the ACALL instruction is a page-miss memory cycle that requires an ALE signal toggle to be used in order to latch a new address
MSB.
FOUR-CYCLE PAGE MODE 1: INC DIRECT (TWO CYCLES) – INC DIRECT (THREE CYCLES)
SYSCLK
ALE
PSEN
PORT 2
HIT
MSB ADDRESS
HIT
LSB ADDRESS
HIT
LSB ADDRESS
STALL
HIT
LSB ADDRESS
PORT 0 05
82
05
86
E0
E0
INC DPL
FOUR-CYCLE PAGE MODE: ACALL – (PAGE MISS)
SYSCLK
ALE
PSEN
PORT 2
HIT
LSB ADDRESS
HIT
LSB ADDRESS
PORT 0
71
33
INC DPS
MISS
MSB ADDRESS
LSB ADDRESS
HIT
LSB ADDRESS
ACALL
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