DS89C420-QCL Datasheet, PDF (66/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
using the MOVX instruction. Any use of this instruction automatically accesses the data area. Although the original 8051 convention
placed all data memory off-chip, the device incorporates 1kB of on-chip data memory. The means for enabling and accessing this
1kB SRAM was covered earlier in this section.
From a software standpoint, the physical location of the data area is not relevant because the same instructions are used. Like the pro-
gram segment, if software accesses a data address that is above the on-chip data area, this access is automatically routed to the
expanded bus. Thus, data or peripherals that are off-chip can be used in conjunction with on-chip memory by selecting addresses
that do not overlap. For example, since the microcontroller has 1kB of on-chip data memory, an MOVX instruction at location 0400h is
directed off-chip through the expanded bus.
The external data memory interface follows the same bus structure as defined for program memory. The page mode enable (PAGEE)
and page mode select (PAGES 1:0) bits control whether the external bus structure follows the nonpage mode, page mode 1, or page
mode 2 scheme. During external data read/write operations, P0 or P2 (depending upon external memory mode) serves as the bidirec-
tional data bus. This port is held in a high-impedance state for external reads from data memory, and driven with data during external
writes to data memory. The read and write strobes used to access external data memory are provided on P3.7 and P3.6, respectively.
EXTERNAL DATA MEMORY INTERFACE—NONPAGE MODE
Data memory is accessed through use of the MOVX instruction. This instruction requires two basic memory cycles: a program-fetch
memory access, and then a read or write memory access. Just like the program memory cycle, a basic internal data memory cycle
contains one system clock, and a basic external data memory cycle contains four system clocks for nonpage mode operation. The
program-fetch memory cycle for an MOVX instruction is no different from any other instruction. The unique timing occurs for the sec-
ond memory cycle when data is accessed.
The ultra-high-speed flash microcontroller allows software to adjust the speed of external data memory access by stretching the mem-
ory bus cycle. The MD2:0 bits contained in the CKCON (8Eh) SFR provide the means to modify the stretch value. This stretch feature
allows the application to dynamically select the minimum (fastest) access time to each data memory peripheral device. The table below
shows the data memory cycle stretch values and their effect on the read and write control signals associated with the external MOVX
memory bus cycle. A stretch machine cycle always contains four system clocks.
As illustrated in Table 6-4, the stretch feature supports eight external data memory access cycles, which can be categorized into three
timing groups. When the stretch value is cleared to 000b, there is no stretch on external data memory access and a MOVX instruction
is completed in two basic memory cycles. When the stretch value is set to 001b, 010b, or 011b, the external data memory access is
extended by 1, 2, or 3 stretch machine cycles, respectively. Note that the 001b stretch value does not add four system clocks to the
RD or WR control signals but instead uses one system clock to create additional address setup and data bus float time and one sys-
tem clock to create additional address and data hold time. When using very slow RAM and peripherals, a larger stretch value (4–7)
can be selected. In this stretch category, one stretch machine cycle (four system clocks) is used to stretch the ALE pulse width, one
stretch machine cycle is used to create additional setup, and one stretch machine cycle is used to create additional hold time.
Table 6-4. Nonpage Mode Data Memory Stretch Values
MD2: MD0 (STRETCH VALUE) STRETCH CYCLES 4X/2X, CD1, CD0 = 100
000
0
0.5
001
1
1
010
2
2
011
3
3
100
7
4
101
8
5
110
9
6
111
10
7
4X/2X, CD1, CD0 = 000
1
2
4
6
8
10
12
14
4X/2X, CD1, CD0 = X10
2
4
8
12
16
20
24
28
4X/2X, CD1, CD0 = X11
2048
4096
8192
12288
16384
20480
24576
28672
_____________________________________________________________________________________________ 66