DS89C420-QCL Datasheet, PDF (10/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
BIT ADDRESSABLE LOCATIONS
In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM
and SFR area. In the scratchpad RAM area, registers 20h to 2Fh are bit addressable. This provides 128 (16 x 8) individual bits avail-
able to software. A bit access is distinguished from a full register access by the type of instruction. Addressing modes are discussed
later in this section. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 4-3 shows details of the on-chip
RAM addressing, including the locations of individual RAM bits.
WORKING REGISTERS
As part of the lower 128 bytes of RAM, there are four banks of working registers (8 bytes each). The working registers are general-purpose
RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently
selected bank is used by any instruction using R0–R7. This allows software to change context by simply switching banks. This is con-
trolled through the program status word register in the next SFR area. The working registers also allow their contents to be used for
indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value stored in R0 (for example) to address
the upper RAM. This value might be the result of another calculation.
STACK
Another use of the scratchpad area is for the programmer’s stack. This area is selected using the stack pointer (SP;81h) SFR. Whenever
a call or interrupt is invoked, the return address is placed on the stack. It also is available to the programmer for variables, etc. Since
the stack can be moved, there is no fixed location within the RAM designated as stack. The stack pointer defaults to 07h upon reset.
The user can then move it as needed. A convenient location would be the upper RAM area (>7Fh), since this is only available indi-
rectly. The SP points to the last used value. Therefore, the next value placed on the stack is put at SP + 1. Each PUSH or CALL incre-
ments the SP by the appropriate value. Each POP or RET decrements as well.
ADDRESS MODES
The DS89C420 uses the standard 8051 instruction set that is supported by a wide range of third-party assemblers and compilers. Like
the 8051, the DS89C420 uses three memory areas. These are program memory, data memory, and registers. The program and data
areas are 64kB each. They extend from 0000h to FFFFh. The register areas are located between 00h and FFh, but do not overlap with
the program and data segments. This is because the ultra-high-speed flash microcontroller uses different modes of addressing to
reach each memory segment. These modes are described below.
Program memory is the area from which all instructions are fetched. It is inherently read only. This is because the 8051 instruction set
provides no instructions that write to this area. Read/write access is for data memory and registers only. No special action is required
to fetch from program memory. Each instruction fetch is performed automatically by the on-chip CPU. In versions that contain on-chip
memory, the hardware decides whether the fetch is on-chip or off-chip based on the address. Explicit addressing modes are needed
for the data memory and register areas. These modes determine which register area is accessed or if off-chip data memory is used.
The ultra-high-speed microcontroller supports eight addressing modes:
• Register addressing
• Direct addressing
• Register indirect addressing
• Immediate addressing
• Register indirect addressing with displacement
• Relative addressing
• Page addressing
• Extended addressing
Five of the eight addressing modes are used to address operands. The remainder are used for program control and branching. When
writing assembly language instructions that use arguments, the convention is “destination, source.” Each mode of addressing is sum-
marized on the following pages. Note that many instructions (such as ADD) have multiple-addressing modes available.
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