DS89C420-QCL Datasheet, PDF (34/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PIS2-0
000
001
010
011
100
101
INTERRUPT PRIORITY LEVEL
No interrupt in progress
Level 0 interrupt in progress
Level 1 interrupt in progress
Level 2 interrupt in progress
Level 3 interrupt in progress
Power-fail warning interrupt in progress
Bit 4
This bit is reserved and reads a logic 1.
SPTA1
Bit 3
Serial Port 1 Transmit Activity Monitor. When set, this bit indicates that data is currently being
transmitted by serial port 1. It is cleared when the internal hardware sets the TI_1 bit. Do not alter
the clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPRA1
Bit 2
Serial Port 1 Receive Activity Monitor. When set, this bit indicates that data is currently being
received by serial port 1. It is cleared when the internal hardware sets the RI_1 bit. Do not alter the
clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPTA0
Bit 1
Serial Port 0 Transmit Activity Monitor. When set, this bit indicates that data is currently being
transmitted by serial port 0. It is cleared when the internal hardware sets the TI_1 bit. Do not alter
the clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
SPRA0
Bit 0
Serial Port 0 Receive Activity Monitor. When set, this bit indicates that data is currently being
received by serial port 0. It is cleared when the internal hardware sets the RI_1 bit. Do not alter the
clock divide control bits (PMR.7-6) while this bit is set or serial port data can be lost.
Timed Access Register (TA)
7
6
SFR C7h
TA.7
TA.6
W-1
W-1
W = Unrestricted write, -n = Value after reset
5
TA.5
W-1
4
TA.4
W-1
3
TA.3
W-1
2
TA.2
W-1
1
TA.1
W-1
0
TA.0
W-1
TA.7–0
Bits 7–0
Timer 2 Control (T2CON)
Timed Access. Correctly accessing this register permits modification of timed access protected
bits. Write AAh to this register first, followed within 3 cycles by writing 55h. Timed access protected
bits can then be modified for a period of 3 cycles measured from the writing of the 55h.
7
6
5
SFR C8h
TF2
EXF2
RCLK
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
TCLK
RW-0
3
EXEN2
RW-0
2
TR2
RW-0
1
C/T2
RW-0
0
CP/RL2
RW-0
TF2
Bit 7
EXF2
Bit 6
Timer 2 Overflow Flag. This flag is set when Timer 2 overflows from FFFFh or the count equal
to the capture register in down count mode. It must be cleared by software. TF2 is only set if RCLK
and TCLK are both cleared to 0.
Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) or timer 2 underflow/overflow
causes this flag to set based on the CP/RL2 (T2CON.0), EXEN2 (T2CON.3), and DCEN
(T2MOD.0) bits (see the following table). If set by a negative transition, this flag must be cleared to
0 by software. Setting this bit in software or detection of a negative transition on the T2EX pin forces
a timer interrupt if enabled.
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