DS89C420-QCL Datasheet, PDF (36/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Timer 2 Mode (T2MOD)
7
6
5
4
3
2
1
0
SFR C9h
—
—
—
—
—
—
T2OE
DCEN
R-1
R-1
R-1
R-1
R-1
R-1
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
T2MOD 7–2
Bits 7–2
Reserved. Read data is 1.
T2OE
Bit 1
Timer 2 Output Enable. This bit enables/disables the clock output function of the T2 pin (P1.0).
When set (= 1), Timer 2 drives the T2 pin with a clock output if C/(T2CON.1) = 0. For this setting,
Timer 2 rollovers do not cause interrupts. When clear (= 0), the T2 pin functions as either a standard
port pin or as a counter input for Timer 2.
DCEN
Bit 0
Down Count Enable. This bit, in conjunction with the T2EX (P1.1) pin, controls the direction that
Timer 2 counts in 16-bit autoreload mode.
DCEN
1
1
0
T2EX
1
0
X
DIRECTION
Up
Down
Up
Timer 2 Capture LSB (RCAP2L)
7
6
5
SFR CAh
RCAP2L.7
RCAP2L.6
RCAP2L.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
RCAP2L.4
RW-0
3
RCAP2L.3
RW-0
2
RCAP2L.2
RW-0
1
RCAP2L.1
RW-0
0
RCAP2L.0
RW-0
RCAP2L.7–0
Bits 7–0
Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured
in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured
in autoreload mode.
Timer 2 Capture LSB (RCAP2H)
7
6
5
SFR CBh
RCAP2H.7 RCAP2H.6 RCAP2H.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
RCAP2H.4
RW-0
3
RCAP2H.3
RW-0
2
RCAP2H.2
RW-0
1
RCAP2H.1
RW-0
0
RCAP2H.0
RW-0
RCAP2H.7–0
Bits 7–0
Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured
in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is con-
figured in autoreload mode.
Timer 2 LSB (TL2)
7
6
5
SFR CCh
TL2.7
TL2.6
TL2.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
TL2.4
RW-0
3
TL2.3
RW-0
2
TL2.2
RW-0
1
TL2.1
RW-0
0
TL2.0
RW-0
TL2.7–0
Bits 7–0
Timer 2 LSB. This register contains the least significant byte of Timer 2.
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