DS89C420-QCL Datasheet, PDF (83/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Crystal
Oscillator
4X/2X
CTM
Clock
Multiplier
Divide-by-1024
MUX
System
Clock
Ring
Enable
Ring
Oscillator
CD0
CD1
Selector
Figure 7-2. System Clock Sources
The oscillator divide ratios of 0.25, 0.5 and 1 are also used to provide standard baud rate generation for the serial ports through a
forced divide-by-12 input clocks (TxMH,TxM = 00b, x = 1, 2, or 3) to the timers. When in divide-by-1024 mode, in order to allow a quick
response to incoming data on a serial port, the system utilizes the switchback mode to automatically revert to divide-by-1 mode when-
ever a start bit is detected. This automatic switchback is only enabled during divide-by-1024 mode and all other clock modes are unaf-
fected by interrupts and serial port activity. See power management mode for more details.
Use of the divide-by-0.25 or 0.5 option through the clock divide control bits requires that the crystal multiplier be enabled and the spe-
cific system clock multiply value be established by the 4X/2X bit in the PMR register. The multiplier is enabled by the CTM (PMR.4) bit
but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/2X
bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system
has moved back to the divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered
when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previ-
ous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in the multiplier startup
counter. During the multiplier startup period, the CKRY bit remains cleared and the CD1 and CD0 clock controls cannot be set to 00b.
The CTM bit is cleared to a logic 0 on all resets. Figure 7-2 (System Clock Sources) gives a simplified description of the generation of
the system clocks. Specifics of hardware restrictions associated with the use of the 4X/2X, CTM, CKRY, CD1, and CD0 bits are out-
lined in the SFR description.
The microcontroller provides two modes (other than operating) that allow power conservation. They are similar, but have different mer-
its and drawbacks. These modes are idle and stop. In the original 8051, the stop mode is called power-down. These modes are invoked
in the same manner as the original 8051 series.
Idle Mode
Idle mode suspends all CPU processing by holding the program counter in a static state. No program values are fetched and no pro-
cessing occurs. This saves considerable power versus full operation. The virtue of idle mode is that it uses half the power of the oper-
ating state, yet reacts instantly to any interrupt conditions. All clocks remain active so the timers, watchdog, serial port, and power mon-
itor functions are all working. Since all clocks are running, the CPU can exit the idle state using any of the interrupt sources.
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