DS89C420-QCL Datasheet, PDF (51/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 00b (ONE CYCLE)
The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusive-
ly on port 0. ALE is used to latch the address MSB only when needed, and PSEN serves as the enable for external program memory.
Note that the one-cycle configuration differs slightly from the two-cycle and four-cycle configurations of the page mode 1 bus structure
in that PSEN does not toggle for consecutive page hits, but stays in the active-low state. To invoke one-cycle page mode 1 operation,
the PAGES 1:0 bits must be set to 00b, followed by the setting of the PAGEE bit. In the 1-cycle Page Mode 1 configuration, a page-hit
memory cycle is one system clock in length, while the page-miss memory cycle requires two system clocks.
In the following first diagram, the CLR C (1 byte, one cycle) instruction fetch occurs during a page-miss memory cycle, followed by the
RRC A instruction (1 byte, 1 cycle) instruction fetch during a page-hit memory cycle. The MUL AB (1 byte, nine cycles) instruction,
which occurs next, requires that the program counter be stalled for eight additional memory cycles so that execution can complete. In
a similar fashion, the DA A (1 byte, two cycles) instruction, which follows the multiply, requires that one stall be inserted.
The second diagram illustrates the memory cycle dependence of some direct instructions on the SFR addressed. The ORL direct, A
is shown for cases where P1 and IE are being addressed.
ONE-CYCLE PAGE MODE 1: (PAGE MISS) – CLR C – MUL AB – DA A – NOP
SYSCLK
ALE
PSEN
PORT 2
MISS HIT HIT
STALLS
LSB ADDRESS
PORT 0
C3 13 A4
D4
CLR C RRC A
MUL AB
HIT STALL HIT HIT
00
DA A NOP
ONE-CYCLE PAGE MODE 1: (PAGE MISS) – ORL DIRECT, A (TWO CYCLES) – ORL DIRECT, A (THREE CYCLES) – NOP
SYSCLK
ALE
PSEN
PORT 2
MISS HIT HIT HIT HIT STALL HIT HIT HIT HIT HIT HIT HIT HIT HIT
LSB
PORT 0
45 90 45 A8
00
ORL, P1, A
MUL AB
NOP
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