DS89C420-QCL Datasheet, PDF (63/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1:
P0: Primary data bus.
P2: Primary address bus, multiplexing the upper byte and lower byte of address.
PAGE MODE 2:
P0: Lower address byte.
P2: Upper address byte is multiplexed with the data byte.
In addition to being accessible to the user application code, the page mode enable and select bits can also be modified while in ROM
loader mode. This allows in-system MOVX read/write access to external memory already connected according to the page mode 1 or
page mode 2 bus structure. Since all resets, including the one generated when exiting ROM loader mode, return to the nonpage mode
external bus structure, user application code must always configure the ACON register appropriately before addressing page mode
external memory. Write access to the ACON register requires using the timed access procedure.
PAGE MODE 1 BUS STRUCTURE
The page mode 1 external bus structure uses P2 as the primary address bus (multiplexing both the most significant byte and least sig-
nificant byte of the address for each external memory cycle), and P0 is used as the primary data bus. This program memory inter-
connect scheme is depicted in Figure 6-4.
PSEN
ALE
PORT 2
DS89C4x0
CK
74F373
LATCH
MSB ADDRESS ₍₈₎
LSB ADDRESS (8)
OE
64kB X 8
MEMORY
CE
PORT 0
DATA BUS
(8)
Figure 6-4 Program Memory Interconnect (Page Mode 1)
During external code fetches, P0 is held in a high-impedance state by the processor. Opcodes are driven by the external memory onto
P0 and latched on the rising edge of PSEN at the end of the external fetch cycle.
• A page miss occurs when the most significant byte of the subsequent address is different from the last address. The exter
nal memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
• A page hit occurs when the most significant byte of the subsequent address does not change from the last address. The exter-
nal memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr [7:0] of the 16-bit address while the most significant address byte is held in the external address latch-
es. PSEN, RD, and RD strobe accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits.
63 _____________________________________________________________________________________________