DS89C420-QCL Datasheet, PDF (92/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
When an interrupt condition occurs, the processor indicates this by setting a flag bit. This flag bit cannot alone cause an interrupt, and
is set regardless of whether the interrupt is enabled. Most flags must be cleared manually by software. However, IE0 and IE1 are
cleared automatically by hardware upon vectoring to the service routine if the interrupt was edge-triggered. In level-triggered mode,
the IE0 or IE1 flags will follow the state of the pin. Flags TF0 and TF1 are always cleared automatically when the service routine is vec-
tored to. Refer to the individual bit descriptions for more details.
Each source must be individually enabled in order to generate CPU interrupts. Each interrupt source has an independent enable, as
shown in Table 9-1. In order for the processor to acknowledge the interrupt and vector to the ISR, the enable all bit (IE.7: EA) must be
set to globally enable interrupt sources. Clearing the EA bit to a logic 0 disables all interrupts, regardless of the individual interrupt
enables. The power-fail warning interrupt source is the only exception, requiring only its individual enable bit be set (WDCON.5: EPFI)
to be recognized by the CPU. The EA bit has no effect on the power-fail interrupt.
INTERRUPT SOURCES
The interrupt sources present on the ultra-high-speed microcontroller can broken into several categories: external, timer-based, serial
communication, and power-fail. Each type is described in the following pages. Interrupt sources are evaluated during the final memo-
ry cycle of each instruction to determine whether and which interrupt is serviced. If the interrupt source goes active after this evalua-
tion, it is not considered until the final memory cycle of the next instruction.
External Interrupts
The ultra-high-speed microcontroller has six external interrupt sources. These include the standard two interrupts of the 8051 archi-
tecture and four new sources. The original interrupts are INT0 and INT1. These are active-low and can be programmed to be edge- or
level-sensitive. The detection mode for each source is controlled through TCON register bits IT0 and IT1, respectively. When ITx = 0,
the interrupt is triggered by a logic 0 on the appropriate interrupt pin. The interrupt condition remains in effect as long as the pin is low.
When ITx = 1, the interrupt is pseudo-edge-triggered. This means that the interrupt is activated, if on successive samples the pin is
found to be in a low state, indicating that a falling edge occurred. Since the external interrupts are sampled, the pin driver of an edge-
triggered interrupt should hold both the high and then the low condition for at least two system clock cycles (each) to ensure detec-
tion. This means maximum sampling frequency on any interrupt pin is one-fourth of the system clock frequency.
It is important to note that level-sensitive interrupts are not latched. This is most important if using other interrupts of equal or higher
priority, because the level-sensitive interrupt request may not receive immediate service by the processor. A level-sensitive interrupt
request is missed unless the condition is held until it can be serviced.
The remaining four external interrupts are similar in nature, with two differences. First, the four new interrupts are edge-detect only. They
do not have level-detect modes. Second, INT2 and INT4 are positive-edge sensitive instead of negative-edge sensitive. All associat-
ed bits and flags operate the same and have the same polarity as the original two. A logic 1 indicates the presence of a condition, not
the logic state of the pin.
If the power management mode is utilized, the designer must remember that detection of edge-triggered interrupts is defined in rela-
tion to the system clock (= 1024 oscillator clock cycles). This means that it requires 2048 external clock cycles before detecting that
an edge has just occurred. As a result, the latency for these interrupts is much longer in power management mode.
Timer Interrupts
The ultra-high-speed flash microcontroller incorporates three 16-bit programmable timers, each of which can generate an interrupt,
and a programmable watchdog timer. The three 16-bit programmable timers operate in the same manner as the 80C52. Each timer
has an independent interrupt enable, flag, vector, and priority. The watchdog timer also has its own interrupt enable, flag, and priority.
Timers 0 and 1 set their respective interrupt flags when the timer overflows from a full condition, depending on its mode. This flag is
set regardless of the interrupt enable state. If the interrupt is enabled, this event generates a call to the corresponding interrupt vec-
tor. For timers 0 and 1, the flags are cleared when the processor jumps to the interrupt vector. Thus, these flags are not available for
use by the interrupt service routine (ISR), but are available outside of the ISR and in applications that do not acknowledge the inter-
rupt (i.e., jump to the vector). If the interrupt is not acknowledged, then software must manually clear the flag bit. In addition to having
an interrupt flag for an overflow condition (as is the case for timers 0 and 1), timer 2 has a second interrupt flag (EXF2) that is associ-
ated with detection of a falling edge on the T2EX (P1.1) pin. When timer 2 has been configured in capture mode (CP/RL2 = 1, EXEN2
= 1) or autoreload mode (CP/RL2 = 0, EXEN2 = 1, DCEN = 0), a negative transition on T2EX causes the EXF2 interrupt flag to be set.
For timer 2 interrupts, jumping to the interrupt vector does not clear either of the flags. Instead, software must ascertain which flag
caused the interrupt and clear it manually. Timer 0 and 1 flag bits reside in the TCON register. Timer 2 flag bits reside in the T2CON
register. The interrupt enables and priorities for timers 0, 1, and 2 reside in the IE and IP0, IP1 registers.
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