DS89C420-QCL Datasheet, PDF (123/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
The microcontroller also matches on any address that corresponds to the broadcast address. This is the logical OR of the SADDR and
SADEN registers, with any zeros defined as don’t cares. In most cases, the broadcast address is FFh.
The multiprocessor communication is always enabled. However, the SADEN registers default to 00h, which means all address bits are
“don’t care,” so all match. Thus, if no multiprocessor communication is used, these registers can be ignored.
SECTION 13: TIMED-ACCESS PROTECTION
The ultra-high-speed microcontroller uses a protection feature called timed access to prevent accidental writes to critical SFR bits.
These bits could cause a system failure or prevent the watchdog timer from doing its job if improperly written. The timed access
involves opening a timing window during which the protected bit can be modified. If the window is opened correctly, it remains open
long enough to alter one protected register. This section explains which bits are protected, why, and how to use the timed-access fea-
ture.
PROTECTED BITS
Bits that are protected by the timed-access feature are shown below. Only critical function bits unique to the ultra-high-speed micro-
controller are protected, ensuring code compatibility with the original 80C51 or 80C52. A full description of the function of each bit is
provided in Section 4:
WDCON.0
WDCON.1
WDCON.3
WDCON.6
EXIF.0
ACON.5
ACON.6
ACON.7
ROMSIZE.0
ROMSIZE.1
ROMSIZE.2
ROMSIZE.3
FCNTL.0
FCNTL.1
FCNTL.2
FCNTL.3
RWT
EWT
WDIF
POR
BGS
PAGES0
PAGES1
PAGEE
RMS0
RMS1
RMS2
RMS3
FC0
FC1
FC2
FC3
Reset watchdog timer
Watchdog reset enable
Watchdog interrupt flag
Power-on reset flag
Bandgap select
Page mode select bit 0
Page mode select bit 1
Page mode enable
Program memory size select bit 0
Program memory size select bit 1
Program memory size select bit 2
Program RAM enable
Flash command bit 0
Flash command bit 1
Flash command bit 2
Flash command bit 3
PROTECTION SCHEME
Each bit mentioned above is protected against an accidental write by requiring the software to perform a procedure before writing the
bit. Timed access requires the software to write two specific values to the timed-access register during two consecutive instruction
cycles. The values AAh, then 55h, must be written in consecutive instructions to the TA register at SFR location C7h. If the writes are
performed correctly, the write-access window opens for three memory cycles. During this window, the software may modify a protect-
ed bit. The suggested code to open a timed-access window is:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
The procedure to modify a timed-access-protected bit begins by writing the value AAh to the timed-access register (TA;C7h). The value
55h must then be written to the timed-access register within three memory cycles of writing AAh. This opens a three memory-cycle win-
dow, after the write of 55h, during which any timed-access protected bits may be modified. Failure to complete any of the required
steps also requires the procedure to begin again, starting with the write of AAh to the timed-access register. Attempts to modify timed-
access-protected bits after the window has closed are ignored. This is regardless of whether any bits were modified. Figure 13-1 illus-
trates a number of examples of correct and incorrect use of the timed-access procedure.
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