DS89C420-QCL Datasheet, PDF (7/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Working Registers
The first 32 bytes of the scratchpad RAM can be used as four banks of eight working registers for high-speed data movement. Using
four banks, software can quickly change context by changing to a different bank. In addition to the accumulator, the working registers
are commonly used as data source or destination. Some of the working registers can also be used as pointers to other RAM locations
(indirect addressing).
Program Counter
The program counter (PC) is a 16-bit value that designates the next program address to be fetched. On-chip hardware automatically
increments the PC value to move to the next program memory location.
Address/Data Bus
The device addresses a 64kB program and 64kB data memory area that resides in a combination of internal and external memory. When
external memory is accessed, ports 0 and 2 are used as a multiplexed address and data bus. Three external memory bus structures
are supported. The nonpage mode (traditional 8051) bus structure provides the address MSB on port 2 and multiplexes port 0 between
address LSB and data. The page mode 1 bus structure uses port 0 exclusively for data and multiplexes port 2 between address MSB
and address LSB. The page mode 2 bus structure uses port 0 exclusively for address LSB and multiplexes port 2 between address MSB
and data. These addressing modes are detailed later.
Watchdog Timer
The watchdog timer provides a supervisory function for applications that cannot afford to run out of control. The watchdog timer is a
programmable, free-running timer. If allowed to reach the termination of its count, if enabled, the watchdog resets the CPU software
must prevent this by clearing or resetting the watchdog prior to its timeout.
Power Monitor
A bandgap reference and analog circuitry are incorporated to monitor the power-supply conditions. When VCC begins to drop out of
tolerance, the power monitor issues an optional early warning power-fail interrupt. If power continues to fall, the power monitor invokes
a reset condition. This remains until power returns to normal operating voltage. The power monitor also functions on power-up, hold-
ing the microcontroller in a reset state until power is stable.
Interrupts
The device is capable of evaluating 13 interrupt sources simultaneously. Each interrupt has an associated interrupt vector, flag, prior-
ity, and enable. These interrupts can be globally enabled or disabled.
Timing Control
The microcontroller provides an on-chip oscillator for use with an external crystal. This can be bypassed by injecting a clock source
into the XTAL1 pin. The clock source is used to create machine cycle timing (four clocks), ALE, PSEN, watchdog, timer, and serial baud-
rate timing. In addition, an on-chip ring oscillator can be used to provide an approximately 10MHz clock source. A frequency multipli-
er feature is included, which can be selected by SFR control to multiply the input clock source by either two or four. This allows lower
frequency (and cost) crystals to be used while still allowing internal operation up to the full 33MHz limit.
Flash Memory
On-chip program memory is implemented in flash memory. This can be programmed in-system with the standard 5V V_CC supply
through a serial port (in-system) using a built-in program memory loader, or by a standard flash or EPROM programmer. Full pro-
gramming details are given in Section 15.
A memory management unit (MMU) and other hardware supports any of the three programming methods. The MMU controls program
and data memory access, and provides sequencing and timing controls for programming of the on-chip program memory. There is
also a separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and other flash
options.
The full on-chip program memory range can be fetched by the processor automatically. Reset routines and all interrupt vectors are
located in the lower 128 bytes of the on-chip program memory area.
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