DS89C420-QCL Datasheet, PDF (84/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Software can invoke the idle mode by setting the IDLE bit in the PCON register at location 87h. The bit is located at PCON.0. The
instruction that executes this step is the last instruction prior to freezing the program counter. Once in idle, all resources are preserved.
There are two ways to exit the idle mode. First, any interrupt (that is enabled) will cause an exit. This results in a jump to the appropri-
ate interrupt vector. The IDLE bit in the PCON register is cleared automatically. Upon returning from this vector using the RETI instruc-
tion, the next address is the one immediately after the instruction that invoked the idle state.
The idle mode can also be removed using a reset. Any of the three reset sources can do this. On receiving the reset stimulus, the CPU
is placed in a reset state and the idle condition cleared. When the reset stimulus is removed, software begins execution as for any
reset. Since all clocks are active, there is no delay after the reset stimulus is removed. Note that if enabled, the watchdog timer con-
tinues to run during idle and must be supported.
Stop Mode
Stop mode is the lowest power state available. This is achieved by stopping all on-chip clocks, resulting in a fully static condition. No
processing is possible, timers are stopped, and no serial communication is possible. Software can invoke stop mode by setting the
STOP bit in the PCON register at location 87h. The bit is located at PCON.1. Processor operation halts on the instruction that sets the
STOP bit. The internal amplifier that excites the external crystal is disabled, halting crystal oscillation in stop mode. Stop mode takes
precedence if application code attempts to set both the STOP and IDLE bits. However, doing this is not suggested. Table 7-1 shows
the state of the processor pins in idle and stop modes.
Stop mode can be exited in two ways. First, like the 8052 microcontrollers, a nonclocked interrupt such as the external interrupts or
the power-fail interrupt can be used. Clocked interrupts, such as the watchdog timer, internal timers, and serial ports do not operate
in stop mode. Note that the bandgap reference must be enabled in order to use the power-fail interrupt to exit stop mode, which
increases stop mode current. Processor operation resumes with the fetching of the interrupt vector associated with the interrupt that
caused the exit from stop mode. When the interrupt service routine is complete, an RETI returns the program to the instruction imme-
diately following the one that invoked the stop mode.
A second method of exiting stop mode is with a reset. The watchdog timer reset is not available as a reset source because no timers
are running in stop mode. An external reset by the RST pin unconditionally exits the device from stop mode. If the BGS bit is set, the
device provides a reset while in stop mode if V_CC should drop below the VRST level. If the BGS bit is 0, then a dip in power below
V_RST does not cause a reset. For example, if V_CC drops to a level of V_RST -0.5V, then returns to the full level, no reset is generated.
For this reason, use of the bandgap reference is recommended if a brownout condition is possible in stop mode. If power fails com-
pletely (V_CC = 0V), then a power-on reset is still performed when V_CC is reapplied, regardless of the state of the BGS bit. Processor
operation resumes execution from address 0000h like any other reset.
Table 7-1. Pin States in Power-Saving Modes
DEVICE EXECUTION
Internal
External nonpage
External page mode 1
External page mode 2
External (any)
MODE
Idle or stop
Idle
Idle
Idle
Stop
ALE
1
1
1
1
1
PSEN
1
1
1
1
1
P0
Port data²
Latched¹
Latched¹
Latched⁵
Port data ²
P1
Port data²
Port data²
Port data²
Port data²
Port data²
1_{Port exhibits opcode following instruction that sets the idle bit.}
2_{Port reflects data stored in corresponding port SFR. Port 0 functions as an open-drain output in this mode.}
3_{Port exhibits address MSB of opcode following instruction that sets the idle bit.}
4_{Port reflects data stored in corresponding port SFR. In this mode, the port uses weak pullups.}
5_{Port exhibits address LSB of opcode following instruction that sets the idle bit.}
P2
Port data²
Latched³
Latched⁵
Latched¹
Port data⁴
P3
Port data²
Port data²
Port data²
Port data²
Port data²
Ring Oscillator Wake-Up From Stop
A typical low-power application is to keep the processor in stop mode most of the time. Periodically, the system wakes up (using an
external interrupt), takes a reading of some condition, and then returns to sleep. The duration of full-power operation is as short as pos-
sible. One disadvantage to this method is that the clock must be restarted prior to performing a meaningful operation. This startup peri-
od is a waste of time and power since no work can be performed. The ultra-high-speed flash microcontroller provides an alternative.
_____________________________________________________________________________________________ 84