DS89C420-QCL Datasheet, PDF (45/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
ANL direct, A
ORL direct, A
DJNZ Rn, direct
52h
42h
D8h-DFh
<addr7-0>
<addr7-0>
<addr7-0>
2 or 3
2 or 3
4
3-Byte Instructions
Three-byte instructions require a minimum of three cycles since each byte fetch requires one memory cycle. The first byte, the opcode,
instructs the CPU on how to handle the next two bytes. Most 3-byte instructions involve comparison or branching, but not all. Just like
the 2-byte instructions, certain 3-byte instructions may require 1 extra memory cycle when operating on the PSW, SP, DPS, IE, EIE, IP0,
IP1, EIP0, or EIP1 register. Following are examples of 3-byte instructions.
OPCODE
LJMP addr16
02h
MOV dptr, #data16 90h
MOV direct, direct 85h
JBC bit, rel
10h
DJNZ direct, rel D5h
OPERAND(s)/LOCATION(s)
<addr15-8><addr7-0>
<data15-8><data7-0>
<addr7-0><addr7-0>
<addr7-0><addr7-0>
<addr7-0><addr7-0>
NO. Of CYCLES
3
3
3 or 4
4 or 5
5
NONPAGE MODE EXTERNAL TIMING
The ultra-high-speed flash microcontroller defaults to a nonpage mode external memory interface. The nonpage mode bus structure
requires four system clock cycles per memory cycle. In the nonpage mode, the ALE signal latches the address LSB on each program
fetch. When the cycle count of an instruction exceeds the byte count, “dummy” fetches are performed each cycle until instruction exe-
cution is complete. The following diagrams demonstrate the basic timing for nonpage mode instruction execution.
The first diagram below shows the execution of the DA A instruction (1 byte, two cycles) followed by execution of the RRC A (1 byte,
one cycle) instruction. When a code fetch is made from a different 256-byte page, the new address MSB is presented on port 2.
The second diagram below shows the execution of the INC direct instruction (2 bytes) for the cases where an extra memory cycle is
not (INC DPL) and is (INC DPS) required.
NONPAGE MODE: DA A – RRC A
SYSCLK
ALE
PSEN
PORT 2
MSB ADDRESS
MSB ADDRESS
PORT 0
LSB
D4
LSB
13
LSB
13
LSB
DA A
NONPAGE MODE: INC DIRECT (2 CYCLES) – INC DIRECT (3 CYCLES)
SYSCLK
ALE
PSEN
PORT 2
MSB ADDRESS
PORT 0 05 LSB
82
LSB
05
LSB
86
RRC A
LSB
E0
LSB
E0
INC DPL
INC DPS
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