DS89C420-QCL Datasheet, PDF (108/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
OSC INPUT TO TIMER
CLK MODE TIMER INPUT
DIVIDE-BY-1 OSC / 2
2X
OSC / 2
4X
OSC / 2
PMM ( / 1024) OSC / 2048
C/T2 = T2CON.1 = 0
T2 = P1.0
T2OE = T2MOD.1
T2EX = P1.1
EXEN2 = T2CON.3
0
78
15
TL2
TH2
TR2 =
T2CON.2
RCAP2L RCAP2H
0
78
15
DIVIDE-
BY-2
EXF2 =
T2CON.6
TIMER 2
INTERRUPT
T2 FREQUENCY OUT = TIMER CLOCK INPUT / (2 x (65536—RCAP2H, RCAP2L))
Figure 11-8. Timer/Counter 2 Clock Out Mode Time–Base Selection
The input clock selection is independent for each timer and the default is 12 oscillator clocks per timer tick. The control bits for the
time-base selection (TxM, TxMH) are located in the clock control register (CKCON;8Eh) and the clock-mode register (CKMOD;96h).
The TxM and TxMH bits for each of the timers enable input clock selections of the system clock divided by 4 and the system clock
divided by 1, respectively. When TxMH is set to a logic 1, the associated TxM bit for that timer is ignored. Note that, when operating
in the default system clock mode, the system clock is the same frequency as the oscillator clock. System clock mode selection is con-
trolled by the CD1, CD0 bits of the PMR register. See the PMR register description and the CPU timing section for more information on
how to modify the system clock. As described earlier, timer 2 does, however, automatically switch to two oscillator clocks per tick when
configured for baud-rate generation or clock-output mode. When the time base is derived from an external source (i.e., the T0, T1, or
T2 pins), the timer operates at the frequency of the external source and is not affected by the setting of the TxM or TxMH bits. The only
limitation is that the external source frequency can be no faster than one-fourth of the main system clock frequency. Use of power man-
agement-mode changes the input clock to the timers in a way that does not exactly follow any of the guidelines set forth to this point.
Tables 11-2 and 11-3 show the resulting timer input clock for the various system clock modes and timer control bit setting. Table 11-2
pertains only to timer 2 in the baud-rate generation or clock-output mode.
Table 11-2. Timers 0, 1, 2 Input Clock Frequency
SYSTEM CLOCK MODE
Crystal multiply mode 4X
Crystal multiply mode 2X
Divide-by-1 (default)
Power-management mode
(divide-by-1024)
PMR REGISTER BITS
4X/2X, CD1, CD0
100
000
X01, X10
X11
TIMERS 0, 1, 2
INPUT CLOCK FREQUENCY
TxMH,TxM = 00
TxMH,TxM = 01
TxMH,TxM = 1x
OSC / 12
OSC / 1
OSC / 0.25
OSC / 12
OSC / 2
OSC / 0.5
OSC / 12
OSC / 4
OSC / 1
OSC / 3072
OSC / 1024
OSC / 1024
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