DS89C420-QCL Datasheet, PDF (125/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
A transient occurs while the op code is being fetched for the first instruction. The transient causes 1 bit of the op code in the first instruc-
tion to be read as a 0 instead of 1. The resulting program is what the microcontroller would actually execute:
TABLE_READ:
C2D2 80 0A 00
C2D5 79 FF
C2D7 78 90
C2D9
C2DA
C2DB
C2DC
C2DD
E0
F6
06
A3
D9 C2 D9
SJMP
MOV
MOV
LOOP:
MOVX
MOV
INC
INC
DJNZ
0BH
R1, #0FFH
R0, #90H
A, @DPTR
@R0, A
R0
DPTR
R1, LOOP
;RELATIVE JUMP BY 10 LOCATIONS
;LOAD COUNTER
;DESTINATION POINTER
;READ DATA BYTE
;STORE IT IN RAM
;NEXT TABLE LOCATION
;NEXT DATA VALUE
;NEXT BYTE OR DONE ?
The resulting jump is to address C2DE. This is not even a real op code, but would be treated as such. The resulting fetch is the value
C2 D9. This is the op code for CLR D9h. The bit-addressable location D9h corresponds to the EWT. If the timed-access procedure did
not prevent it, this errant instruction would disable the watchdog. Note that the program execution is completely lost now. Real op
codes are being replaced by operands, data, and garbage. In the ultra-high-speed microcontroller, the watchdog recovers from this
state as soon as it times out, since it could not have been disabled in this way.
In the ultra-high-speed microcontroller it is very hard to contrive a situation that accidentally disables the watchdog. Note, the timed
access prevents accidentally writing a bit. It can not prevent accidentally calling the correct code that writes a bit. This is much more
unlikely, however.
SECTION 14: INSTRUCTION SET DETAILS
Details of flags modified by each instruction are located in Section 4.
MNEMONIC
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A,
direct
ADDC A, @Ri
ADDC A,#data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
INC DPTR
DEC A
DEC Rn
DEC direct
DEC @Ri
MUL AB
DIV AB
INSTRUCTION CODE
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
1
n2 n1
n0
0
0
1
0
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
0
0
1
0
0
1
1
i
0
0
1
0
0
1
0
0
d7 d6 d5 d4 d3 d2 d1 d0
0
0
1
1
1
n2 n1 n0
0
0
1
1
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
0
0
1
1
0
1
1
i
0
0
1
1
0
1
0
0
d7 d6 d5 d4 d3 d2 d1 d0
1
0
0
1
1
n2 n1 n0
1
0
0
1
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
1
0
0
1
0
1
1
i
1
0
0
1
0
1
0
0
d7 d6 d5 d4 d3 d2 d1 d0
0
0
0
0
0
1
0
0
0
0
0
0
1
n2 n1 n0
0
0
0
0
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
0
0
0
0
0
1
1
i
1
0
1
0
0
0
1
1
0
0
0
1
0
1
00
0
0
0
1
1
n2 n1 n0
0
0
0
1
0
1
0
1
a7 a6 a5 a4 a3 a2 a1 a0
0
0
0
1
0
1
1
i
1
0
1
0
0
1
0
0
1
00
0
0
1
0
0
HEX
28-2F
25
Byte 2
26-27
24
Byte 2
38-3F
35
Byte 2
36-37
34
Byte 2
98-9F
95
Byte 2
96-97
94
Byte 2
04
08-0F
05
Byte 2
06-07
A3
14
18-1F
15
Byte 2
16-17
A4
84
BYTE
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
CYCLE
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2*
2
1
1
1
2*
2
9
10
EXPLANATION
(A) = (A) + (Rn)
(A) = (A) + (direct)
(A) = (A) + ((Ri))
(A) = (A) + #data
(A) = (A) + (C) + (Rn)
(A) = (A) + (C) + (direct)
(A) = (A) + (C) + ((Ri))
(A) = (A) + (C) + #data
(A) = (A) - (C) - (Rn)
(A) = (A) - (C) - (direct)
(A) = (A) - (C) - ((Ri))
(A) = (A) - (C) - #data
(A) = (A) + 1
(Rn) = (Rn) + 1
(direct) = (direct) + 1
((Ri)) = ((Ri)) + 1
(DPTR) = (DPTR) + 1
(A) = (A) - 1
(Rn) = (Rn) - 1
(direct) = (direct) -1
((Ri)) = ((Ri)) - 1
(B15–8 ), (A7–0 ) = (A) x (B)
(B15–8 ), (A7–0 ) = (A) / (B)
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