DS89C420-QCL Datasheet, PDF (82/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Power-On Reset
When V_CC is applied to a system, the device holds itself in reset until power is within tolerance and stable. The internal bandgap ref-
erence provides a highly accurate and stable means of detecting power-supply levels. It requires no external circuits to accomplish
this. As power rises, the processor stays in a reset state until V_CC > V_RST. As V_CC rises above VRST, internal analog circuits detect
this and activate the on-chip crystal oscillator. On-chip hardware then counts 65536 oscillator clocks. During this count, V_CC must
remain above V_RST. or the process restarts. If an off-chip clock source is used, clock counting still begins once V_CC > V_RST. This count
period is used to make certain that power is within tolerance and that the oscillator has time to stabilize. This provides a very controlled
and predictable startup condition.
Once the 65536 count period has elapsed, the reset condition is removed automatically, and software execution begins at the reset
vector location of 0000h. Software is able to detect the power-on reset condition using the power-on reset (POR) flag. POR is located
at WDCON.6. This bit is high to indicate that a power-on reset has occurred. It should then be cleared by software.
The complete power cycle operation is shown in Figure 7-1. Note that the interrupt threshold is fixed, but the interrupt itself is option-
al. Reset thresholds are also fixed and the reset operation is transparent. It requires no external components and no action by software
to control reset operation.
Bandgap Select
The bandgap is normally disabled automatically upon entering stop mode to provide the lowest power state. Since the bandgap is
inactive, there can be no power-fail interrupt and no power-fail reset, similar to a traditional 8051.
If the use of the power-fail features is desired in stop mode, the BGS bit (EXIF, 91h) can be used. When set to a logic 1 by software,
the bandgap reference and associated power monitor circuits remain active in stop mode. The price of this feature is higher power-
supply current requirements. In stop mode with the bandgap reference disabled (default), the processor draws approximately 10µA.
With the bandgap enabled, it draws approximately 75µA.
BGS allows the user to decide whether the control circuitry and its associated power consumption are needed. If the application is
such that power does not fail while in stop, or if it does not matter that power fails, the BGS should be set to 0 (default). If power can
fail at any time and cause problems, the BGS should be set to 1.
Watchdog Wake-Up From Idle
The watchdog wake-up is more of an application than a feature. It allows a system to enter the idle mode for power savings, then to
wake up periodically to sample the external world. Idle mode is a low-power state described below. Any of the programmable timers
can perform this function, but the watchdog allows a much longer period to be selected. At 33MHz, the maximum watchdog timeout
is over 2s. This contrasts with 23.8ms using the 16-bit timers. Software that uses the watchdog as a wake-up alarm should enable only
the watchdog interrupt and not the reset. Note that the watchdog cannot be used to wake the system while in stop mode since no
clocks are running. Stop mode is described in the Power Management Summary section below.
POWER SAVING
The ultra-high-speed flash microcontroller is implemented using full CMOS circuitry for low-power operation. It is fully static, so the
clock speed can be run down to DC. Like other CMOS, the power consumption is also a function of operating frequency. Although the
microcontroller is designed for maximum performance, it also provides improved power versus work relationships compared with stan-
dard 8051 devices. These topics are discussed in detail in the following pages.
Clock Divide Control
The programmable clock divide control bits CD1 and CD0 (PMR, C4h) provide the processor with the ability to adapt to different crys-
tals and also to slow the system clocks, providing lower power operation when required. An on-chip crystal multiplier allows the ultra-
high-speed flash microcontroller to operate at two or four times the crystal frequency by setting the 4X/2X bit and is enabled by set-
ting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024. When used with a 10MHz crystal, for
example, the processor executes machine cycle in times ranging from 25ns (divide-by-0.25) to 102.4µs (divide-by-1024) and main-
tains a highly accurate, serial port baud rate while allowing the use of more cost-effective, lower-frequency crystals. Although the clock
divide control bits can be written at any time, certain hardware features have been provided to enhance the use of these clock con-
trols to guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. The 01b setting of
CD1 and CD0 is reserved and has the same effect as the setting of 10b, which forces the system clock into a divide-by-1 mode. The
ultra-high-speed flash microcontroller defaults to divide-by-1 clock mode on all forms of reset.
When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5: SWB) is also set, the system forces the clock divide
control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts.
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