DS89C420-QCL Datasheet, PDF (18/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
SEL
Bit 0
Power Control (PCON)
Data Pointer Select. This bit selects the active data pointer.
0 = Instructions that use the DPTR use DPL and DPH.
1 = Instructions that use the DPTR use DPL1 and DPH1.
7
6
5
4
SFR 87h
SMOD_0
SMOD0
OFDF
OFDE
RW-0
RW-0
RW-0*
RW-0*
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
3
GF1
RW-0
2
GF0
RW-0
1
STOP
RW-0
0
IDLE
RW-0
SMOD_0
Bit 7
SMOD0
Bit 6
OFDF
Bit 5
OFDE
Bit 4
GF1
Bit 3
GF0
Bit 2
STOP
Bit 1
IDLE
Bit 0
Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the serial baud rate doubling
function for Serial Port 0.
0 = Serial Port 0 baud rate is that defined by baud rate generation equation.
1 = Serial Port 0 baud rate is double that defined by baud rate generation equation.
Framing Error Detection Enable. When clear (= 0), SCON1.7 and SCON0.7 serve as mode select
bit SM0 for the respective serial ports. When set (= 1), SCON1.7 and SCON0.7 report whether a
Framing Error has been detected.
Oscillator Fail Detect Flag. When OFDE = 1, this flag will be set if a reset condition is generated
due to oscillator failure. This bit is cleared on a power-on reset and is unchanged by other reset
sources. This bit must be cleared by software.
Oscillator Fail Detect Enable. When set (= 1), the oscillator fail detect circuitry and flag generation
are enabled. An oscillator fail detection occurs if the crystal oscillator falls below ~20kHz. An oscillator
fail detection does not occur if the oscillator is halted through software setting of the STOP bit
(PCON.1) or when running from the internal ring oscillator source. When clear (= 0), the oscillator
fail detect circuitry is disabled.
General-Purpose User Flag 1. This is a general-purpose flag for software control.
General-Purpose User Flag 0. This is a general-purpose flag for software control.
Stop Mode Select. Setting this bit stops program execution, halts the CPU oscillator and internal
timers, and places the CPU in a low-power mode. This bit always be reads as a 0.
Setting this bit causes the CTM bit (PMR.4) to be cleared. Setting both the
STOP bit and the IDLE bit causes the device to enter stop mode; however, doing this is not advised.
Idle Mode Select. Setting this bit stops program execution but leaves the CPU oscillator, timers,
serial ports, and interrupts active. This bit is always read as a 0. Setting both the STOP bit and
the IDLE bit causes the device to enter stop mode; however, doing this is not advised.
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