DS89C420-QCL Datasheet, PDF (53/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 2 EXTERNAL TIMING—PAGES 1:0 = 11b
The page mode 2 external bus structure multiplexes port 2 between address MSB and data. The address LSB is provided exclusive-
ly on port 0. ALE is used to latch the address MSB only when needed, and PSEN serves as the enable for external program memory.
To invoke page mode 2 operation, the PAGES 1:0 bits must be set to 11b, followed by the setting of the PAGEE bit. In the page mode
2 configuration, a page-hit program memory cycle is two system clocks in length, while the page-miss program memory cycle requires
four system clocks. All data memory cycles are four system clocks in length.
The first diagram below shows the fetch of the CLR C instruction (1 byte, 1 cycle) during a page-miss memory cycle, followed by the
fetch of the RRC A instruction (1 byte, one cycle) during a page-hit memory cycle. The next instruction, XCH A, @R0 (1 byte, three
cycles), requires three memory cycles to execute, so two stall cycles must be inserted for it to complete prior to the next instruction
being read.
The second diagram below illustrates the LJMP (3 bytes, three cycles) instruction, whose destination address is on a different 256-byte
page than the LJMP instruction, thus resulting in a page-miss memory cycle.
PAGE MODE 2: (PAGE MISS) – CLR C – RRC A – XCH A, @R0
SYSCLK
ALE
PSEN
PORT2
MISS
MSB
HIT
HIT
stall
C3
13
C6
stall
HIT
PORT0
LSB
LSB
CLR C
LSB
RRC A
LSB Address
XCH A, @R0
PAGE MODE 2: (PAGE MISS) – LJMP addr16 – (PAGE MISS)
HIT
LSB
SYSCLK
ALE
PSEN
PORT2
PORT0
MISS
MSB
LSB
HIT
HIT
02
50
00
MISS
MSB
LSB
LSB
LJMP addr16
LSB
HIT
HIT
LSB
LSB
COMPARISON TO THE 8051
The original 8051 needed 12 clocks per machine cycle and most instructions executed in either one or two machine cycles. Thus,
except for the MUL and DIV instructions, the 8051 used either 12 or 24 clocks for each instruction. Furthermore, each machine cycle
in the 8051 used two memory fetches. In many cases the second fetch was a dummy, and the extra clock cycles were wasted.
The ultra-high-speed microcontroller uses one clock per memory (or machine) cycle. Where there were primarily one- and two-cycle
instructions before, an instruction on the ultra-high-speed microcontroller may take between one and ten cycles. The divide instruction,
for example, requires 10 cycles. Note however, that the 10 cycles needed for the DIV AB instruction can be executed at one clock per
cycle (10 x 1 = 10 total clock cycles). The instruction is executed 4.8 times faster than the original 8051 architecture which required
four cycles at a rate of 12 clocks per cycle (4 x 12 = 48 total clock cycles). Each instruction is at least four times faster, with the high-
est throughput improvement being 24 times that of the original 8051 architecture.
53 _____________________________________________________________________________________________