DS89C420-QCL Datasheet, PDF (90/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Watchdog Timer Reset
The ultra-high-speed flash microcontroller incorporates a safety feature to prevent corrupted software from controlling the CPU. This
feature is called the watchdog timer. It is a free-running timer with a programmable interval. The watchdog supervises the processor
operation by requiring software to clear the timer before an overflow occurs. If the timer is enabled and software fails to clear it before
this interval expires, the ultra-high-speed flash microcontroller is placed into a reset state. The reset state maintains for 13 clock cycles.
Once the reset is removed, the processor resumes execution at address 0000h. Software can determine if a reset is caused by a watch-
dog timeout by checking the watchdog timer reset flag (WTRF) in the WDCON register. This flag is cleared by software only.
Oscillator Fail-Detect Reset
Oscillator fail-detect circuitry monitors the on-chip oscillator activity. When enabled, this circuit causes a reset if the oscillator frequen-
cy falls below ~20kHz, and holds the chip in reset until the oscillator frequency rises back above ~20kHz. The circuitry is enabled by
setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit can be cleared by software or by the occurrence of a power-fail reset. A reset
caused by an oscillator failure sets the OFDF (PCON.5) flag bit to a logic 1. This flag can be cleared by software or by a power-on
reset. The oscillator fail-detect circuitry utilizes the internal ring oscillator to clock the chip into the reset state and maintain the reset
state while the oscillator is below the minimum frequency. Note, however, that the circuitry does not force a reset when the oscillator is
purposely stopped when software invokes stop mode.
External Reset
If the RST input is asserted to logic 1, the device is forced into a reset state. An external reset is accomplished by holding the RST pin
high at least four clock cycles while the oscillator is running. Once the reset state is invoked, it is maintained as long as RST is assert-
ed at logic 1. When the RST is removed, the processor exits the reset state within four clock cycles and begins execution at address
0000h.
If an RST is applied while the processor is in the stop mode, the RST causes the oscillator to begin running and forces the program
counter to 0000h. The reset delay is 65,536 clock cycles to allow the oscillator to stabilize.
The RST pin is a bidirectional I/O. If a reset is caused by a power fail reset, a watchdog timer reset, an oscillator fail detect reset, or
an internal system reset, a positive output level is also generated at the RST pin. This reset level is asserted as long as an internal reset
is asserted. The drive capability of this I/O port may be insufficient if the RST pin is connected to a RC reset circuit. Connecting the
RST pin to a capacitor would not affect the internal reset condition.
Determining The Cause Of a Reset
During the debugging process, it might be necessary to isolate the cause of a device reset. Because resets are initiated by a limited
number of sources, it is relatively easy to determine their source by interrogating the flag bits associated with the reset sources. The
table below lists the reset sources and flag bits. Although no flag bits are associated with the internal system reset generated by issu-
ing a system reset or complement bank-select flash command, it is unlikely that these would occur unintentionally, given that the flash
command bits (FCNTL.3-0) require a timed-access write.
Reset Source Flag Associations
RESET SOURCE
Power-on reset
Watchdog reset
Oscillator fail-detect reset
Internal system reset
External reset
FLAG BIT
POR – WDCON.6
WTRF – WDCON.2
OFDF – PCON.5
None
None
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