DS89C420-QCL Datasheet, PDF (24/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
RGMD
Bit 2
RGSL
Bit 1
BGS
Bit 0
clock source or switchover from the ring oscillator to the crystal oscillator can occur.
Ring Mode Status. This status bit indicates the current clock source for the device. This bit is
cleared to 0 after a power-on reset, and unchanged by all other forms of reset.
0 = Device is operating from the external crystal or oscillator.
1 = Device is operating from the ring oscillator.
Ring Oscillator Select. When set (= 1), this bit enables operation using the on-chip ring oscillator
as the clock source until the oscillator warm-up period has completed (CKRY = 1). Using the ring
oscillator to resume from stop mode allows almost instantaneous startup. This bit is cleared to 0
after a power-on reset, and unchanged by all other forms of reset.
0 = Device operation is held until completion of the crystal oscillator warm-up delay period.
1 = The device begins operating from the ring oscillator and switch over to the crystal oscillator
upon completion of the warm-up delay period.
Bandgap Select. This bit enables/disables the bandgap reference during stop mode. Disabling
the bandgap reference provides significant power savings in stop mode, but sacrifices the ability
to perform a power-fail interrupt or power-fail reset while stopped. This bit can only be modified
with a timed access procedure.
Timer and Serial Port Clock Mode Register (CKMOD)
7
6
5
4
3
2
1
0
SFR 96h
—
—
T2MH
T1MH
T0MH
—
—
—
RW-1
RW-1
RW-0
RW-0
RW-0
RW-1
RW-1
RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
0 = The bandgap reference is disabled in stop mode but functions during normal operation.
1 = The bandgap reference operates in stop mode.
T2MH
Bit 5
Timer 2 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 2 and the T2M bit (CKCON.5) setting is ignored. When clear (= 0), the input
clock for Timer 2 is selected using the T2M bit.
T1MH
Bit 4
Timer 1 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 2 and the T1M bit (CKCON.4) setting is ignored. When clear (= 0), the input
clock for Timer 2 is selected using the T1M bit.
Serial Port 0 Control (SCON0)
7
6
5
SFR 98h
SM0/FE_0
SM1_0
SM2_0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
REN_0
RW-0
3
TB8_0
RW-0
2
RB8_0
RW-0
1
TI_0
RW-0
0
RI_0
RW-0
T0MH
Bit 3
SM0–2
Bits 7, 6, 5
Timer 0 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 2 and the T0M bit (CKCON.3) setting is ignored. When clear (= 0), the input
clock for Timer 2 is selected using the T0M bit.
Serial Port Mode. These bits control the mode of serial port 0. In addition the SM0 and SM2_0 bits
have secondary functions as shown.
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