DS89C420-QCL Datasheet, PDF (40/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Extended Interrupt Priority 1 (EIP1)
SFR F1h
7
6
—
—
R-1
R-1
5
4
3
2
1
0
—
MPWDI
MPX5
MPX4
MPX3
MPX2
R-1
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Bits 7–5
Reserved. Read data is 1.
MPWDI
Bit 4
Most significant priority select bit for watchdog interrupt. Most significant bit of the bit pair
MPWDI, LPWDI (EIP0.4) that designates priority level for the watchdog interrupt.
MPX5
Bit 3
Most significant priority select bit for external interrupt 5. Most significant bit of the bit pair
MPX5, LPX5 (EIP0.3) that designates priority level for external interrupt 5.
MPX4
Bit 2
Most significant priority select bit for external interrupt 4. Most significant bit of the bit pair
MPX4, LPX4 (EIP0.2) that designates priority level for external interrupt 4.
MPX3
Bit 1
Most significant priority select bit for external interrupt 3. Most significant bit of the bit pair
MPX3, LPX3 (EIP0.1) that designates priority level for external interrupt 3.
MPX2
Bit 0
Most significant priority select bit for external interrupt 2. Most significant bit of the bit pair
MPX2, LPX2 (EIP0.0) that designates priority level for external interrupt 2.
Interrupt priority level for the above sources is assigned using one bit from register EIP1 (F1h) and
one bit from EIP0 (F8h). The bit from EIP1 serves as the most significant bit and the bit from EIP0
serves as the least significant bit, in forming a 2-bit binary number. This number represents the pri
ority level. Higher priority interrupts, when enabled, take precedence over lower priority sources.
The power-fail warning interrupt source is assigned Priority Level 4.
Most Significant Priority Select Bit Levels
MP (EIP1.x)
0
0
1
1
LP (EIP0.x)
0
1
0
1
PRIORITY LEVEL
0 (natural priority)
1
2
3 (high priority)
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