DS89C420-QCL Datasheet, PDF (70/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
NONPAGE MODE DATA MEMORY TIMING
The first diagram below shows execution of the MOVX instruction from internal program memory with stretch value = 0 assigned
(MD2:0 = 000b). Note that the internal memory cycles consist of one system clock while the external memory cycles always consist of
four system clocks.
The second diagram illustrates the same MOVX instruction with a default stretch value (MD2:0 = 001b). The stretch cycle (four system
clocks) is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR pulse
duration, and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is added
to the duration of the RD or WR pulse.
NONPAGE MODE: MOVX (TWO CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2
MOVX MSB
PORT0
MOVX INST
LSB
DATA
MOVX
Data Access
INSTRUCTIONS
NONPAGE MODE: MOVX (THREE CYCLES)
SYSCLK
ALE
PSEN
WR / RD
PORT2
MOVX MSB
PORT0
MOVX INST
MOVX LSB
MOVX DATA
MOVX Data Access
(1 _{Stretch Cycle)}
INSTRUCTIONS
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