DS89C420-QCL Datasheet, PDF (25/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Serial Port Mode Functions
SM0
0
0
0
1
1
1
1
SM1
0
0
1
0
0
1
1
SM2
0
1
X
0
1
0
1
MODE
0
0
1
2
2
3
3
FUNCTION
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous with multiprocessor
communication
Asynchronous
Asynchronous with multiprocessor
communication
LENGTH (BITS)
8
8
10
11
PERIOD
See PMR register
See PMR register
Timer 1 or 2 baud rate equation
See PMR register
11
See PMR register
11
Timer 1 or 2 baud rate equation
11
Timer 1 or 2 baud rate equation
SM0/FE_0
Bit 7
SM1_0
Bit 6
SM2_0
Bit 5
REN_0
Bit 4
TB8_0
Bit 3
RB8_0
Bit 2
TI_0
Bit 1
RI_0
Bit 0
Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
serial port 0. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit do not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
No alternate function.
Multiple CPU Communications. The function of this bit is dependent on the serial port 0 mode.
Mode 0: Selects period for synchronous serial port 0 data transfers.
Mode 1: When set, reception is ignored (RI_0 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in modes 2 and 3.
This prevents the RI_0 bit from being set, and an interrupt being asserted, if the 9th bit received is not 1.
Receiver Enable. This bit enable/disables the serial port 0 receiver shift register.
0 = Serial port 0 reception disabled.
1 = Serial port 0 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 0
modes 2 and 3.
9th Received Bit State. This bit identifies that state of the 9th reception bit of received data in
serial port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop
bit. RB8_0 is not used in mode 0.
Transmitter Interrupt Flag. This bit indicates that data in the serial port 0 buffer has been
completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other
modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software.
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial port
0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set
after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0
is set after the last sample of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
7
6
5
SFR 99h
SBUF0.7
SBUF0.6
SBUF0.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
SBUF0.4
RW-0
3
SBUF0.3
RW-0
2
SBUF0.2
RW-0
1
SBUF0.1
RW-0
0
SBUF0.0
RW-0
SBUF0.7–0
Bits 7–0
Serial Data Buffer 0. Data for serial port 0 is read from or written to this location. The serial
transmit and receive buffers are separate registers, but both are addressed at this location.
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