DS89C420-QCL Datasheet, PDF (85/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
If the ring select (RGSL) is enabled, the microcontroller can exit stop mode running from an internal ring oscillator. Upon receipt of an
interrupt, this oscillator can start instantaneously, allowing software execution to begin immediately while the oscillator is stabilizing.
Ring oscillator execution cannot be used to support accurate baud-rate generation or precise timer/counter operations. Once 65,536
clock cycles have been detected, the CPU automatically switches to the normal oscillator as its clock source. However, if the required
interrupt response is very short, the software can reenter stop mode before the crystal is even stable. In this case, stop mode can be
invoked and both oscillators are stopped.
Speed Reduction
The ultra-high-speed flash microcontroller is a fully CMOS 8051-compatible device. It can use significantly less power than other 8051
versions, because it is more efficient. As an average, software runs 10 times faster on the ultra-high-speed flash microcontroller than
on other 8051 derivatives. Thus, the same job can be accomplished by slowing down the crystal by a factor of 10. For example, an
existing 8051 design that runs at 12MHz can run at approximately 1.2MHz on the ultra-high-speed flash microcontroller. At this reduced
speed, the ultra-high-speed microcontroller has lower power consumption than an 8051, yet performs the same job.
Using the 10X factor, Table 7-2 shows the approximate speed at which the ultra-high-speed flash microcontroller can accomplish the
same work as an 8051. The exact improvement varies depending on the actual instruction mix. Available crystal speeds must also be
considered. Refer to Section 14 for information on instruction timing.
Table 7-2. Crystal vs. MIPS Comparison
ORIGINAL 8051
CRYSTAL SPEED (MHz)
16
20
24
33
40
MIPS
1.3
1.6
2.0
2.7
3.3
ULTRA-HIGH-SPEED FLASH MICROCONTROLLER
CRYSTAL SPEED (MHz)
1.6
2.0
2.4
3.3
4.0
Power Management Modes
Power consumption in CMOS microcontrollers is a function of operating frequency. The power management mode (PMM) feature allows
software to dynamically match operating frequency and current consumption with the need for processing power. Instead of the default
one clock per machine cycle, PMM utilizes 1024 clocks per cycle to conserve power.
Several special features have been added to enhance the function of the PMM. The switchback feature allows the device to almost
instantaneously return to divide-by-1 mode upon detection of an enabled external interrupt or the receipt of a falling edge on a serial
port receiver pin. The advantages of this become apparent when one calculates the increased interrupt service time of a device oper-
ating in PMM. In addition, a device operating in PMM would normally be unable to sample an incoming serial transmission to proper-
ly receive it. The switchback feature, explained below, allows a device to return to divide-by-4 operation in time to receive incoming
serial port data and process interrupts with no loss in performance.
A status register (STATUS;C5h) prevents the device from accidentally reducing the clock rate during the servicing of an external inter-
rupt or serial port activity. This register can be interrogated to determine whether an interrupt is in progress, or if serial port activity is
occurring. Based on this information the software can delay or reject a planned change in the clock divider rate.
In addition, the ultra-high-speed flash microcontroller has the capability to operate from the internal ring oscillator during normal oper-
ation, not only during the crystal warmup period. Table 7-3 summarizes the new control bits associated with the power management
features.
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