DS89C420-QCL Datasheet, PDF (62/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Internal Memory Cycles
XTAL1
ALE
PSEN
Port 0
Port 2
Ext Memory Cycle
C1 C2 C3 C4
Ext Memory Cycle
C1 C2 C3 C4
LSB Add
Data LSB Add
Data
MSB Add
MSB Add
Figure 6-3. External Program Memory Access (Nonpage Mode and CD1:0 = 10b)
As illustrated in that same figure, ALE is deasserted when executing an internal memory fetch. The microcontroller provides a pro-
grammable user option (ALEON bit = PMR.2) to turn on the ALE signal during internal program memory operation. The ALE signal is
automatically enabled for external code fetches, independent of the setting of this bit. PSEN is asserted only for external code fetch-
es, and is inactive during internal execution.
PROGRAM MEMORY INTERFACE—PAGE MODES
Page mode retains the basic external circuitry requirements as the original 8051 external memory interface, but modifies the
address/data roles of P0 and P2 in order to achieve the most efficient single-cycle external operation possible. The functions of ALE
and PSEN are also altered to support page mode operation.
Page mode is enabled by setting the PAGEE (ACON.7) bit to a logic 1. Clearing the PAGEE bit disables the page mode and returns
to the traditional external bus structure of the 8051 (nonpage mode). Page mode is supported in two external bus structures. The page
mode select bits (PAGES1:0) contained in the ACON register determine the external bus structure and the number of system clocks
per basic memory cycle. The following table summarizes the four options available through the PAGES bits. The first three selections
all represent the page mode 1 external bus structure, but with different memory cycle timings. The last configuration (PAGES = 11b)
selects the page mode 2 bus structure.
Table 6-3. Page Mode Select
EXTERNAL ADDRESSING
MODE
Page mode 1 (1 cycle)
Page mode 1 (2 cycle)
Page mode 1 (4 cycle)
Page mode 2
PAGES1:PAGES0
00
01
10
11
CLOCKS PER MEMORY CYCLE
PAGE HIT
PAGE MISS
1
2
2
4
4
8
2*
4
Note: External data memory accesses always require four clock cycles, regardless of page hit or page miss.
EXTERNAL BUS STRUCTURE
PAGE MODE 1
PAGE MODE 1
PAGE MODE 1
PAGE MODE 2
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