DS89C420-QCL Datasheet, PDF (106/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Up/Down-Count Autoreload Timer/Counter
The up/down autoreload counter option is selected by the DCEN (T2MOD.0) bit, and is illustrated in Figure 11-6. When DCEN
(T2MOD.0) is set to a logic 1, timer 2 counts up or down as controlled by the state of pin T2EX (P1.1). T2EX causes upward counting
when a logic 1 is applied and down counting when a logic 0 is applied. When DCEN = 0, timer 2 only counts up.
When an upward counting overflow occurs, the value in RCAP2L and RCAP2H loads into TL2 and TH2. In the down-count direction,
an underflow occurs when TL2 and TH2 match the values in RCAP2L and RCAP2H, respectively. When an underflow occurs, FFFFh
is loaded into TL2 and TH2 and counting continues.
Note that, in this mode, the overflow/underflow output of the timer is provided to an edge-detection circuit as well as to the TF2 bit
(T2CON.7). This edge-detection circuit toggles the EXF2 bit (T2CON.6) on every overflow or underflow. Therefore, the EXF2 bit behaves
as a 17th bit of the counter, and may be used as such.
Baud-Rate Generator
Timer 2 can be used to generate baud rates for serial port 0 in serial mode 1 or 3. Baud-rate generator mode is invoked by setting
either the RCLK or TCLK bit in the T2CON register to a logic 1, as illustrated in Figure 11-7. In this mode, the timer continues to func-
tion in autoreload mode, but instead of setting the interrupt flag TF2 (T2CON.7) and potentially causing an interrupt, the overflow gen-
erates the shift clock for the serial port function. As in normal autoreload mode, an overflow causes RCAP2L and RCAP2H to be trans-
ferred into T2L and T2H, respectively. Note that, when RCLK or TCLK is set to 1, timer 2 is forced into 16-bit autoreload mode, regard-
less of the CP/RL2 bit.
As explained above, the timer itself cannot set the TF2 interrupt flag and, therefore, cannot generate an interrupt. However, if EXEN2
(T2CON.3) is set to 1, a 1 to 0 transition on the T2EX (P1.1) pin causes the EXF2 (T2CON.6) interrupt flag to be set. If enabled, this
causes a timer 2 interrupt to occur. Therefore, in this mode, the T2EX pin may be used as an additional external interrupt, if desired.
EXTERNAL OSCILLATOR
INPUT TO TIMER
CLK MODE SYSCLK
DIVIDE-BY-1 OSC / 1
2X
OSC / 0.5
4X
OSC / 0.25
T2 = P1.0
TR2 = T2CON.2
T2EX = P1.1
T2M = CKCON.5
DIVIDE-
BY-12
0
DIVIDE- 1
BY-4
T2MH = CKMOD.5
(DOWN-COUNTING RELOAD VALUE)
C / T2 = T2CON.1
0
0FFH
0FFH
0
1
CLK ₀
78
15
TL2
TH2
1
COUNT DIRECTION
(1 = UP, 0 = DOWN)
0
78
15
RCAP2L R AP2H
(UP-COUNTING RELOAD VALUE)
TF2 =
T2CON.7
TIMER 2
INTERRUPT
EXF2 =
T2CON.6
NOTE: FOR POWER-MANAGEMENT MODE (DIVIDE-BY-1024) OPERATION, THE TIMER INPUT CLOCK TO THE TIMER IS
OSC / 1024 IF EITHER TXM = 1 OR TXMH = 1. OTHERWISE, THE TIMER INPUT IS OSC / 3072.
Figure 11-6. Timer/Counter 2 Autoreload Mode (DCEN = 1)
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