DS89C420-QCL Datasheet, PDF (31/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
SM0/FE_1
Bit 7
Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
serial port 1. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit does not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
SM1_1
Bit 6
No alternate function.
SM2_1
Bit 5
Multiple CPU Communications. The function of this bit is dependent on the serial port 1 mode.
Mode 0: Selects period for synchronous port 1 data transfers.
Mode 1: When this bit is set, reception is ignored (RI_1 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in mode 2 and 3. This
prevents RI_1 from being set, and an interrupt being asserted, if the 9th bit received is not 1.
REN_1
Bit 4
Receive Enable. This bit enables/disables the serial port 1 receiver shift register.
0 = Serial port 1 reception disabled.
1 = Serial port 1 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
TB8_1
Bit 3
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 1
modes 2 and 3.
RB8_1
Bit 2
9th Received Bit State. This bit identifies the state for the 9th reception bit received data in serial
port 1 modes 2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit.
RB8_1 is not used in mode 0.
TI_1
Bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial port 1 buffer has been com-
pletely shifted out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes,
this bit is set at the end of the last data bit. This bit must be manually cleared by software.
RI_1
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Bit 0
port 1 buffer. In serial port mode 1, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1
is set after the last sample of the incoming stop bit subject to the state of SM2_1. In modes 2 and
3, RI_1 is set after the last sample of RB8_1. This bit must be manually cleared by software.
Serial Data Buffer 1 (SBUF1)
7
6
5
SFR C1h
SBUF1.7
SBUF1.6
SBUF1.5
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
4
SBUF1.4
RW-0
3
SBUF1.3
RW-0
2
SBUF1.2
RW-0
1
SBUF1.1
RW-0
0
SBUF1.0
RW-0
SBUF1.7–0
Bits 7–0
Serial Data Buffer 1. Data for serial port 1 is read from or written to this location. The serial
transmit and receive buffers are separate registers, but both are addressed at this location.
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