DS89C420-QCL Datasheet, PDF (38/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
Watchdog Control (WDCON)
7
6
5
4
3
2
SFR D8h
SMOD_1
POR
EPFI
PFI
WDIF
WTRF
RW-0
RT-*
RW-0
RW-*
RT-0
RW-*
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset, * = see description
1
EWT
RT-*
0
RWT
RT-0
SMOD_1
Serial Modification. This bit controls the doubling of the serial port 1 baud rate in modes 1, 2, and 3.
Bit 7
0 = Serial port 1 baud rate operates at normal speed.
1 = Serial port 1 baud rate is doubled.
POR
Bit 6
Power-On Reset Flag. This bit indicates whether the last reset was a power-on reset. This bit is
typically interrogated following a reset to determine if the reset was caused by a power-on reset. It
must be cleared by a timed access write before the next reset of any kind or user software may
erroneously determine that another power-on reset has occurred. This bit is set following a power-
on reset and unaffected by all other resets. This bit automatically cleared when the ROM loader is
invoked.
0 = Last reset was from a source other than a power-on reset.
1 = Last reset was a power-on reset.
EPFI
Bit 5
Enable Power-Fail Interrupt. This bit enables/disables the ability of the internal bandgap
reference to generate a power-fail interrupt when VCC falls below approximately 4.5V. While in stop
mode, both this bit and the bandgap Select bit, BGS (EXIF.0), must be set to enable the power-fail
interrupt.
0 = Power-fail interrupt disabled.
1 = Power-fail interrupt enabled during normal operation. Power-fail interrupt enabled in stop mode
if BGS is set.
PFI
Bit 4
Power-Fail Interrupt Flag. When set, this bit indicates that a power-fail interrupt has occurred. This
bit must be cleared in software before exiting the interrupt service routine, or another interrupt is
generated. Setting this bit in software generate a power-fail interrupt, if enabled. This bit is auto-
matically cleared when the ROM loader is invoked.
WDIF
Bit 3
Watchdog Interrupt Flag. This bit indicates if a watchdog timer event has occurred. The timeout
period of the watchdog timer is controlled by the Watchdog Timer Mode Select bits (CKCON.7-6).
The Watchdog Timer Interrupt Enable bit, EWDI (EIE.4), and Enable Watchdog Timer Reset bit,
EWT (WDCON.1), determine what action is taken. This bit must be cleared in software before
exiting the interrupt service routine, or another interrupt is generated. Setting this bit in software
generates a watchdog interrupt if enabled. This bit can only be modified using a Timed Access
Procedure.
WTRF
Bit 2
Watchdog Timer Reset Flag. When set, this bit indicates that a watchdog timer reset has
occurred. It is typically interrogated to determine if a reset was caused by watchdog timer reset. It
is cleared by a power-on reset but otherwise must be cleared by software before the next reset
of any kind or software can erroneously determine that a watchdog timer reset has occurred.
Setting this bit in software does not generate a watchdog timer reset. If the EWT bit is cleared, the
watchdog timer has no effect on this bit. This bit is automatically cleared when the ROM loader is
invoked.
EWT
Bit 1
Enable Watchdog Timer Reset. This bit enables/disables the generation of a watchdog timer
reset 512 system clocks after the occurrence of a watchdog timeout. This bit can only be modi-
fied using a Timed Access Procedure and is unaffected by all other resets. The default power-on
reset state of EWT is determined by Option Control Register bit 3 (OCR.3) located in flash memo
ry. This bit will automatically be cleared when the ROM loader is invoked.
0 = A watchdog reset is not generated after a watchdog timeout
1 = A watchdog reset is generated 512 system clocks after a watchdog timeout unless RWT is
strobed or EWT is cleared.
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