DS89C420-QCL Datasheet, PDF (8/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 4: PROGRAMMING MODEL
This section provides a programmer’s overview of the ultra-high-speed microcontroller core. It includes information on the memory
map, on-chip RAM, SFRs, and instruction set. The programming model of the ultra-high-speed microcontroller is very similar to that of
the industry-standard 80C52. The memory map is identical. It uses the same instruction set, with improved instruction timing. Several
new SFRs have been added.
MEMORY ORGANIZATION
The ultra-high-speed flash microcontroller, like the 8052, uses several distinct memory areas. These areas include registers, program
memory, and data memory. Registers serve to control on-chip peripherals and as RAM. Note that registers (on-chip RAM) are sepa-
rate from data memory. Registers are divided into three categories including directly addressed on-chip RAM, indirectly addressed on-
chip RAM, and SFRs. The program and data memory areas are discussed in the Memory Map section. The registers are discussed in
the Register Map section.
MEMORY MAP
The ultra-high-speed microcontroller uses a memory-addressing scheme that separates program memory from data memory. Each
area is 64kB beginning at address 0000h and ending at FFFFh, as shown in Figure 4-1. The program and data segments can overlap
since they are accessed in different ways. Program memory is fetched by the microcontroller automatically. These addresses are never
written by software. In fact, there are no instructions that allow the program area to be written. There is one instruction (MOVC) that is
used to explicitly read the program area. This is commonly used to read lookup tables. The data memory area is accessed explicitly
using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is used to access the 64kB of
data memory.
The address and data range of devices with on-chip program and data memory overlap the 64k memory space. When on-chip mem-
ory is enabled, accessing memory in the on-chip range causes the device to access internal memory. Memory accesses beyond the
internal range are addressed externally through ports 0 and 2.
The ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the
device to act as a bootstrap loader for an external flash or nonvolatile SRAM. Secondly, this method can also be used to increase the
amount of available program memory from 64kB to 80kB without bank switching. For more information on this feature, see Section 6.
Program and data memory can also be increased beyond the 64kB limit using bank-switching techniques. This is described in
Application Note 81: Memory Expansion with the High-Speed Microcontroller Family.
REGISTER MAP
The register map is illustrated in Figure 4-2. It is entirely separate from the program and data memory areas mentioned above. A sep-
arate class of instructions is used to access the registers. There are 256 potential register location values. In practice, the ultra-high-
speed microcontroller has 256 bytes of scratchpad RAM and up to 128 SFRs. This is possible since the upper 128 scratchpad RAM
locations can only be accessed indirectly. That is, the contents of a working register (R0 or R1) or the stack pointer designates the RAM
location. A direct reference to one of the lower 128 addresses (0h-7Fh) accesses the scratchpad RAM. A direct reference to one of the upper
128 addresses (80h-FFh) must be an SFR access. In contrast, indirect references can access the entire scratchpad RAM range (0h-FFh).
Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data con-
tents are small. When off-chip RAM is needed, the scratchpad area still provides the fastest general-purpose access. Within the 256
bytes of RAM, there are several special purpose areas. These are described as follows:
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