DS89C420-QCL Datasheet, PDF (116/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
When using timer 2 to generate baud rates, the formula is as follows. Note that the reload value is a 16-bit number, as compared with
timer 1, which uses only 8 bits. A second equation is provided so that the timer 2 reload value can be calculated for a given baud rate.
1
Modes 1, 3 baud rate =
✕
16
Timer 2 input clock frequency
(65536–RCAP2H,RCAP2L)
Number of serial bits /
Number of timer 2 rollovers
Timer 2 rollover
frequency
Timer 2 input clock frequency
RCAP2H, RCAP2L = 65536 –
16 x baud rate
Timer 2 input clock frequency can be found in Table 12-6, and RCAP2H, RCAP2L is the user assigned timer 2 reload value.
SERIAL I/O DESCRIPTION
A detailed description and block diagram of each serial mode is given below. Note that the baud clock input (to the serial I/O control
block) corresponding to the power-management mode has been omitted from each of the block diagrams. Reference the tables ear-
lier in this section for power-management mode baud clock rates. A description of framing-error detection and multiprocessor com-
munication follows this section.
Mode 0
Mode 0 is used to communicate in synchronous, half-duplex format with devices that accept the ultra-high-speed microcontroller as a
master. Figure 12-1 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidirectional data
line (RXD) and one shift clock line (TXD) used for communication. The shift clock is used to shift data into and out of the microcon-
troller and the remote device. Mode 0 requires that the microcontroller is the master, because the microcontroller generates the serial
shift clocks for both directions. As described earlier in the section, the shift clock frequency is a function of the system clock if the SM2
(SCON0.5 or SCON1.5) bit is set to a logic 1.
The RXD signal is used for both transmission and reception. TXD provides the shift clock. Data bits enter and exit least-significant bit
(LSb) first. The baud rate is equal to the shift clock frequency. The relevant UART begins transmitting when any instruction writes to
SBUF0 or SBUF1 (address 99h or C1h). The internal shift register then begins to shift data out. The clock is activated and transfers
data until the 8-bit value is complete. Data is presented just prior to the falling edge of the shift clock (TXD) so that an external device
can latch the data using the rising edge.
The UART begins to receive data when the REN bit in the SCON register (SCON0.4 or SCON1.4) is set to a logic 1 and the RI bit
(SCON0.0 or SCON1.0) is set to a logic 0. This condition tells the UART that there is data to be shifted in. The shift clock (TXD) acti-
vates, and the UART latches incoming data on the rising edge. The external device should therefore present data on the falling edge.
This process continues until 8 bits have been received. The RI bit is automatically set to a logic 1 immediately following the last rising
edge of the shift clock on TXD. This causes reception to stop until the SBUF has been read, and the RI bit cleared. When RI is cleared,
another byte can be shifted in.
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