DS89C420-QCL Datasheet, PDF (43/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
SYSTEM CLOCK DIVIDE CONTROL
The ultra-high-speed microcontroller provides the ability to speed up or slow down the system clock that is used internally by the CPU.
The system clock divide ratio can be configured to 0.25 (4X multiply mode), 0.5 (2X multiply mode), 1 (default), or 1024 (power man-
agement mode) and is controlled by the CD1:0 bits (PMR.7, PMR.6).
To use the crystal multiply mode, the multiplier circuit must be prompted to warmup in the desired 4X or 2X configuration. The 4X/2X
bit defines the crystal multiplying factor. This bit can be altered only from the divide-by-1 (default) mode, while the crystal multiplier is
disabled (CTM = 0). Once the 4X/2X bit has been configured as desired, setting the CTM bit (PMR.4) initiates the crystal multiplier
warmup period. The CTM bit can only be altered when the CD1:0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0.
During the multiplier warmup period the CKRY bit remains cleared and the CD1:0 clock control bits cannot be set to 00b. When the
crystal multiplier circuit has completed the warmup and is ready for use, the CKRY (EXIF.3) bit set to a logic 1. At this point, the CD1:0
bits can be modified to select the multiplier output for use as the internal system clock. Specifics of hardware restrictions associated
with the use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR descriptions. The prescribed sequence for selecting
the the crystal multiplier is as follows:
1) Ensure that the current clock mode is set to divide-by-1 (CD1:0 = 10b) and that RGMD (EXIF.2) = 0.
2) Clear the CTM bit.
3) Put the 4X/2X bit in the desired state.
4) Set the CTM bit.
5) Poll for the CKRY (EXIF.3) bit to be set (= 1). This takes ~65536 external clock cycles.
6) Set CD1:0 = 00b. The frequency multiplier is engaged on the memory cycle following the writing of these bits.
An additional circuit provides a divide-by-1024 clock source that can be selected as the internal system clock. When programmed to
the divide-by-1024 mode, the user may wish to set the switchback bit (PMR.5: SWB) to force the clock divide control bits automatical-
ly back to the divide-by-1 mode whenever the system detects an externally enabled interrupt or an incoming serial port start bit. This
automatic switchback is only enabled during divide-by-1024 mode, and all other clock control settings are unaffected by interrupts and
serial port activity. The power management mode is detailed further in Section 7 (Power Management).
It is important to remember that changing the system clock frequency affects all aspects of system operation, including timers and ser-
ial port baud rates. These effects are detailed in Section 11 (Programmable Timers) and Section 12 (Serial I/O). The following diagram
illustrates the system clock control function.
Figure 5-3. System Clock Sources
CRYSTAL
OSCILLATOR
4X / 2X
CTM
CLOCK
MULTIPLIER
DIVIDE 1024
MUX
00
01, 10
11
SYSTEM
CLOCK
RING
ENABLE
RING
OSCILLATOR
CD0
CD1
SELECTOR
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