DS89C420-QCL Datasheet, PDF (76/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 2 DATA MEMORY TIMING–PAGES 1:0 = 11b (FOUR CYCLES)
All external data memory accesses made using the page mode 2 external bus configuration require four system clocks. The MOVX
timing looks identical to the nonpage mode MOVX timing except that port 2 multiplexes the MSB and the data, while port 0 serves as
the LSB.
DATA MEMORY ACCESS
As mentioned earlier in this section, the ultra-high-speed microcontroller uses the MOVX instruction for data memory access. This
includes off-chip RAM and memory-mapped peripherals needing read/write access. Several aspects of the MOVX operation have been
enhanced as compared to the original 8051. The principal improvements are in the areas of the MOVX timing and the data pointer.
The MOVX instruction is used to generate read/write access to off-chip address locations. It has several addressing modes. The first
uses the MOVX @Ri command to reach a 256-byte block. This instruction uses the value in the designated working register to address
one of 256 locations. The upper byte of the address is supplied by the value in the port 2 latch. A second way to access data is the
data pointer (DPTR). This 16-bit register provides an absolute address for data memory access. 16-bits cover the entire 64kB area.
Thus the DPTR serves as a pointer to memory. Using the DPTR, the relevant instruction is MOVX @DPTR.
The original 8051 contained one DPTR. While this provides access to the entire memory area, it is difficult to move data from one
address to another. The ultra-high-speed microcontroller provides two data pointers. Thus software can load both a source and a des-
tination address. The MOVX instruction uses the active pointer to direct the off-chip address.
The dual data pointers are DPTR0 and DPTR1. DPTR0 is at SFR addresses 82h and 83h. These are the locations used by the original
8051. No modification of standard code is needed to use DPTR0. The new DPTR is located at SFR 84h and 85h. The data pointer select
bit (SEL) chooses the active pointer and is located in bit position 0 of the DPS (86h) SFR. When DPS is set to 0, the DPTR0 is active.
When set to 1, DPTR1 is used. All DPTR-related instructions use the currently selected DPTR for any activity.
Each data pointer (DPTR0, DPTR1) has an associated control bit (ID0, ID1) that determines whether the INC DPTR operation results in
an increment or decrement of the pointer. When the active data pointer ID (increment/decrement) control bit is clear, the INC DPTR
instruction will increment the pointer, whereas a decrement occurs if the active pointer’s ID bit is set when the INC DPTR instruction is
performed.
ID0 = DPS.6
ID1 = DPS.7
Using the dual data pointers for large block copy operations results in substantial code savings versus using a single data pointer,
since one data pointer can be used for the source address and the second pointer can be used as the destination address. The user
switches between data pointers by toggling the SEL bit. One way of accomplishing this is by executing the INC DPS instruction. For
these large-block copy operations, the user must execute this instruction frequently to toggle between DPTR0 and DPTR1. To improve
the speed and efficiency of moving data with dual data pointers, the ultra-high-speed microcontroller contains a toggle select (TSL)
bit. When this TSL bit (DPS.5) is set, execution of certain MOVX instructions automatically toggle the SEL bit in hardware, allowing
removal of the INC DPS instruction and increasing execution speed.
Copying large blocks of data also requires that the source and destination pointers index byte-by-byte through their respective data
ranges. The traditional method for incrementing each pointer is through the use of the INC DPTR instruction. The ultra-high-speed flash
microcontroller provides yet another means of accelerating data transfers with the implementation of an auto increment/decrement bit
(AID). When this AID bit (DPS.4) is set, execution of certain MOVX instructions automatically increments or decrements the active data
pointer.
AUTO-TOGGLE (if TSL = 1)
AUTO-INC/DEC (if AID = 1)
MOVC A, @A+DPTR
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX A, @DPTR
MOVX @DPTR, A
MOVX @DPTR, A
INC DPTR
MOV DPTR, #data16
The following table summarizes the tremendous speed improvements gained through using the dual DPTRs along with autoincrement
and autotoggle features. To properly quantify the speed improvement gained with enhanced data pointer operation versus improve-
ment attributed to the single-cycle core architecture, execution time for the DS80C320 high-speed microcontroller (four-cycle core) has
been included where applicable. For external page mode 1 (PAGES1:0 = 00b) code execution has been assumed. It is unreasonable
to expect that the address MSBs for MOVX read/write operations are the same as the address MSB for code execution. Therefore, one
clock cycle has been added to each MOVX instruction (for data access) and to the instruction that follows the MOVX (for code fetch)
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