DS89C420-QCL Datasheet, PDF (50/139 Pages) Maxim Integrated Products – Ultra-High-Speed Flash Microcontroller User’s Guide

Ultra-High-Speed Flash
Microcontroller User’s Guide
PAGE MODE 1 EXTERNAL TIMING—PAGES 1:0 = 01b (TWO CYCLES)
The page mode 1 external bus structure multiplexes port 2 to provide the address MSB and LSB. Data transactions occur exclusively on port 0. ALE
is used to latch the Address MSB only when needed, and PSEN serves as the enable for external program memory. To invoke two-cycle page mode
1 operation, the PAGES1:0 bits must be set to 01b, followed by the setting of the PAGEE bit. In the two-cycle page mode 1 configuration, a page-hit-
memory cycle is two system clocks in length, while the page-miss memory cycle requires four system clocks.
The first diagram below shows the fetch of the CLR C instruction (1 byte, one cycle) during a page-miss memory cycle, followed by the fetch of the
RRC A instruction (1 byte, one cycle) during a page-hit memory cycle. Since the next instruction, XCH A, @R0 (1 byte, three cycles), requires three
memory cycles to execute, two stall cycles must be inserted for it to complete prior to the next instruction being read.
The second diagram below illustrates the LJMP (3 bytes, three cycles) instruction, whose destination address is on a different 256-byte page than
the LJMP instruction, thus resulting in a page-miss memory cycle.
TWO-CYCLE PAGE MODE 1: (PAGE MISS) – CLR C – RRC A – XCH A, @R0
SYSCLK
ALE
PSEN
PORT 2
MISS
MSB
LSB
HIT
LSB
HIT
LSB
STALL
STALL
HIT
LSB ADDRESS
PORT 0
C3
13
C6
HIT
LSB
CLR C
RRC A
XCH A, @R0
TWO-CYCLE PAGE MODE 1: (PAGE MISS) – LJMP ADDR16 – (PAGE MISS)
SYSCLK
ALE
PSEN
PORT 2
MISS
MSB
LSB
HIT
LSB
HIT
LSB
MISS
MSB
LSB
PORT 0
02
50
00
HIT
LSB
HIT
LSB
LJMP ADDR16
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