MC9S12P128 Datasheet, PDF (96/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12PPIMV1)
2.3.56 Port J Interrupt Flag Register (PIFJ)
Address 0x026F
R
W
Reset
7
PIFJ7
0
1. Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
0
PIFJ6
PIFJ2
0
0
0
0
0
Figure 2-54. Port J Interrupt Flag Register (PIFJ)
Access: User read/write⁽¹⁾
1
0
PIFJ1
PIFJ0
0
0
Table 2-50. PIFJ Register Field Descriptions
Field
Description
7-6, 2-0
PIFJ
Port J interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.3.57 Port AD Data Register (PT0AD)
Address 0x0270
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Altern.
Function
—
—
—
—
—
—
Reset
0
0
0
0
0
0
Figure 2-55. Port AD Data Register (PT0AD)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Access: User read/write⁽¹⁾
1
0
PT0AD1
PT0AD0
AN9
AN8
0
0
Table 2-51. PT0AD Register Field Descriptions
Field
Description
1-0
PT0AD
Port AD general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
S12P-Family Reference Manual, Rev. 1.12
96
Freescale Semiconductor