MC9S12P128 Datasheet, PDF (234/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Figure 7-32. Startup of clock system after Reset
System
Reset
PLLCLK
768 cycles
f_VCORST
)(
LOCK
f_PLL increasing
t_lock
f_PLL=16MHz
f_PLL=32 MHz
SYNDIV $1F (default target f_VCO=64MHz)
POSTDIV $03 (default target f_PLL=f_VCO/4 = 16MHz)
CPU
reset state
vector fetch, program execution
$01
example change
of POSTDIV
7.4.3 Stop Mode using PLL Clock as Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure 7-33. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 7-33. Stop Mode using PLL Clock as Bus Clock
wakeup
CPU ^execution
PLLCLK
LOCK
STOP instruction
t_{STP_REC}
interrupt continue execution
t_lock
7.4.4 Full Stop Mode using Oscillator Clock as Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in Figure 7-34.
S12P-Family Reference Manual, Rev. 1.12
234
Freescale Semiconductor