MC9S12P128 Datasheet, PDF (546/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Detailed Register Address Map
0x0020-0x002F Debug Module (S12SDBG) Map
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0x0028
(3)
R
DBGCCTL
W
0
0
TAG
BRK
RW
RWE
R
0
0
0
0
0
0
0x0029 DBGXAH
W
R
0x002A DBGXAM
Bit 15
14
13
12
11
10
W
R
0x002B DBGXAL
Bit 7
6
5
4
3
2
W
R
0x002C DBGADH
Bit 15
14
13
12
11
10
W
R
0x002D DBGADL
Bit 7
6
5
4
3
2
W
R
0x002E DBGADHM
Bit 15
14
13
12
11
10
W
R
0x002F DBGADLM
Bit 7
6
5
4
3
2
W
1. This represents the contents if the Comparator A or C control register is blended into this address
2. This represents the contents if the Comparator B or D control register is blended into this address
3. This represents the contents if the Comparator B or D control register is blended into this address
Bit 1
0
17
9
1
9
1
9
1
Bit 0
COMPE
Bit 16
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0x0030-0x0033 Reserved
Address Name
Bit 7
R
0
0x0030 Reserved
W
R
0
0x0031 Reserved
W
R
0
0x0032 Reserved
W
R
0
0x0033 Reserved
W
Bit 6
0
0
0
0
Bit 5
0
0
0
0
Bit 4
0
0
0
0
Bit 3
0
0
0
0
Bit 2
0
0
0
0
Bit 1
0
0
0
0
Bit 0
0
0
0
0
0x0034-0x003F Clock Reset and Power Management (CPMU) Map
Address Name
R
0x0034 CPMUSYNR
W
R
0x0035 CPMUREFDIV
W
0x0036
CPMUPOSTDI R
V
W
R
0x0037 CPMUFLG
W
Bit 7
Bit 6
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
RTIF
PORF
Bit 5
0
0
LVRF
Bit 4
0
Bit 3
Bit 2
SYNDIV[5:0]
Bit 1
REFDIV[3:0]
LOCKIF
POSTDIV[4:0]
LOCK
ILAF
OSCIF
Bit 0
UPOSC
S12P-Family Reference Manual, Rev. 1.12
546
Freescale Semiconductor