MC9S12P128 Datasheet, PDF (400/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Serial Peripheral Interface (S12SPIV5)
12.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
12.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
12.3.1 Module Memory Map
The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
0x0000
SPICR1
R
SPIE
W
0x0001
R
0
SPICR2 _W
0x0002
R
0
SPIBR
W
0x0003
SPISR
R SPIF
W
0x0004
R R15
SPIDRH _{W T15}
0x0005
R
R7
SPIDRL _W
T7
0x0006
R
Reserved _W
0x0007
R
Reserved _W
6
SPE
XFRW
SPPR2
0
5
4
3
SPTIE
MSTR
CPOL
0
MODFEN BIDIROE
0
SPPR1
SPPR0
SPTEF
MODF
0
R14
R13
R12
R11
T14
T13
T12
T11
R6
R5
R4
R3
T6
T5
T4
T3
= Unimplemented or Reserved
Figure 12-2. SPI Register Summary
2
CPHA
0
SPR2
0
R10
T10
R2
T2
1
SSOE
SPISWAI
SPR1
0
R9
T9
R1
T1
Bit 0
LSBFE
SPC0
SPR0
0
R8
T8
R0
T0
S12P-Family Reference Manual, Rev. 1.12
400
Freescale Semiconductor