MC9S12P128 Datasheet, PDF (210/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
0x0038
7
6
R
0
RTIE
W
5
4
3
0
0
LOCKIE
2
1
0
0
0
OSCIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-8. S12CPMU Interrupt Enable Register (CPMUINT)
Read: Anytime
Write: Anytime
Table 7-4. CRGINT Field Descriptions
Field
7
RTIE
4
LOCKIE
1
OSCIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
7.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)
This register controls S12CPMU clock selection.
0x0039
R
W
Reset
7
PLLSEL
1
6
5
0
PSTP
4
3
2
1
0
PRE
PCE
RTI
OSCSEL
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-9. S12CPMU Clock Select Register (CPMUCLKS)
0
COP
OSCSEL
0
Read: Anytime
Write: Only possible when PROT=0 (CPMUPROT register).
PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: write anytime.
COPOSCSEL: write anytime in normal mode until CPMUCOP write once is taken. If COPOSCSEL was
cleared by UPOSC=0 (entering full stop mode with COPOSCSEL=1 or insufficient OSCCLK quality),
then COPOSCSEL can be set again once.
Write anytime in special mode.
S12P-Family Reference Manual, Rev. 1.12
210
Freescale Semiconductor