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MC9S12P128 Datasheet, PDF (209/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Table 7-3. CPMUFLG Field Descriptions (continued)
Field
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
1
OSCIF
0
UPOSC
Description
Low Voltage Reset Flag â LVRF is set to 1 when a low voltage reset occurs. This ï¬ag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
PLL Lock Interrupt Flag â LOCKIF is set to 1 when LOCK status bit changes. This ï¬ag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
Lock Status Bit â LOCK reï¬ects the current state of PLL lock condition. Writes have no effect. While PLL is
unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL
stabilization time tlock.
0 VCOCLK is not within the desired tolerance of the target frequency.
fPLL = fVCO/4.
1 VCOCLK is within the desired tolerance of the target frequency.
fPLL = fVCO/(POSTDIV+1).
Illegal Address Reset Flag â ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for
details. This ï¬ag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
Oscillator Interrupt Flag â OSCIF is set to 1 when UPOSC status bit changes. This ï¬ag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
Oscillator Status Bit â UPOSC reï¬ects the status of the oscillator. Writes have no effect. While UPOSC=0 the
OSCCLK going to the MSCAN module is off. Entering full stop mode UPOSC is cleared.
0 The Oscillator is off or oscillation is not qualiï¬ed by the PLL.
1 The Oscillator is qualiï¬ed by the PLL.
NOTE
The adaptive spike ï¬lter uses the VCO clock as a reference to continuously
qualify the external oscillator clock. Because of this, the PLL is always
active and a valid PLL conï¬guration is required for the system to work
properly. Furthermore, the adaptive spike ï¬lter is used to determine the
status of the external oscillator (reï¬ected in the UPOSC bit). Since this
function also relies on the VCO clock, losing PLL lock status (LOCK=0,
except for entering pseudo stop mode) means losing the oscillator status
information as well (UPOSC=0).
7.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)
This register enables S12CPMU interrupt requests.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
209
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