MC9S12P128 Datasheet, PDF (162/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
Table 6-7. DBGTCR Field Descriptions (continued)
Field
3–2
TRCMOD
0
TALIGN
Description
Trace Mode Bits — See 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In
Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 6-8.
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
TRCMOD
00
01
10
11
Table 6-8. TRCMOD Trace Mode Bit Encoding
Description
Normal
Loop1
Detail
Compressed Pure PC
6.3.2.4 Debug Control Register2 (DBGC2)
Address: 0x0023
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 6-9. DBGC2 Field Descriptions
1
0
ABCM
0
0
Field
Description
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 6-10.
ABCM
00
01
10
Table 6-10. ABCM Encoding
Description
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
Match 0 mapped to comparator A/B inside range: Match1 disabled.
Match 0 mapped to comparator A/B outside range: Match1 disabled.
S12P-Family Reference Manual, Rev. 1.12
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