MC9S12P128 Datasheet, PDF (45/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Device Overview MC9S12P-Family
Table 1-12. Interrupt Vector Locations (Sheet 2 of 3)
Vector Address⁽¹⁾
Vector base+ $F0
Vector base+ $EE
Vector base + $EC
Vector base+ $EA
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base + $E2
Vector base+ $E0
Vector base+ $DE
Vector base+ $DC
Vector base + $DA
Vector base + $D8
Vector base+ $D6
Vector base + $D4
Vector base + $D2
Vector base + $D0
Vector base + $CE
Vector base + $CC
to
Vector base + $CA
Vector base + $C8
Vector base + $C6
Vector base + $C4
to
Vector base + $BC
Vector base + $BA
Vector base + $B8
Vector base + $B6
Vector base + $B4
Vector base + $B2
Vector base + $B0
Interrupt Source
RTI timeout interrupt
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
TIM timer overflow
TIM Pulse accumulator A overflow
TIM Pulse accumulator input edge
SPI
SCI
ATD
Port J
CCR
Mask
Local Enable
Wake up Wakeup
from STOP from WAIT
I bit
CPMUINT (RTIE)
7.6 Interrupts
I bit
TIE (C0I)
No
Yes
I bit
TIE (C1I)
No
Yes
I bit
TIE (C2I)
No
Yes
I bit
TIE (C3I)
No
Yes
I bit
TIE (C4I)
No
Yes
I bit
TIE (C5I)
No
Yes
I bit
TIE (C6I)
No
Yes
I bit
TIE (C7I)
No
Yes
I bit
TSRC2 (TOF)
No
Yes
I bit
PACTL (PAOVI)
No
Yes
I bit
PACTL (PAI)
No
Yes
I bit
SPICR1 (SPIE, SPTIE)
No
Yes
I bit
SCICR2
Yes
Yes
(TIE, TCIE, RIE, ILIE)
Reserved
I bit
ATDCTL2 (ASCIE)
Yes
Yes
Reserved
I bit PIEJ (PIEJ7-PIEJ6, PIEJ2-
Yes
Yes
PIEJ0)
Reserved
Oscillator status interrupt
I bit
CPMUINT (OSCIE)
No
No
PLL lock interrupt
I bit
CPMUINT (LOCKIE)
No
No
FLASH error
FLASH command
CAN wake-up
CAN errors
CAN receive
CAN transmit
Reserved
I bit FERCNFG (SFDIE, DFDIE)
I bit
FCNFG (CCIE)
I bit
CANRIER (WUPIE)
I bit CANRIER (CSCIE, OVRIE)
I bit
CANRIER (RXFIE)
I bit
CANTIER (TXEIE[2:0])
No
No
No
Yes
8.4.7 Interrupts
S12P-Family Reference Manual, Rev. 1.12
45
Freescale Semiconductor