MC9S12P128 Datasheet, PDF (213/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.8 S12CPMU RTI Control Register (CPMURTI)
This register selects the timeout period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts
in Stop Mode.
0x003B
R
W
Reset
7
RTDEC
0
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
0
0
0
0
0
Figure 7-11. S12CPMU RTI Control Register (CPMURTI)
1
RTR1
0
Read: Anytime
Write: Anytime
NOTE
A write to this register start or re-starts the RTI time-out period. A change
of the RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
0
RTR0
0
Table 7-8. CPMURTI Field Descriptions
Field
Description
7
RTDEC
6–4
RTR[6:4]
3–0
RTR[3:0]
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 7-9
1 Decimal based divider value. See Table 7-10
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 7-
9 and Table 7-10.
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 7-9 and Table 7-10 show all possible divide values selectable by the
CPMURTI register.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
213