MC9S12P128 Datasheet, PDF (204/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.1 Module Memory Map
The S12CPMU registers are shown in Figure 7-3.
Addres
s
Name
0x0034
CPMU
SYNR
R
W
0x0035
CPMU
REFDIV
R
W
0x0036
CPMU
POSTDIV
R
W
R
0x0037 CPMUFLG
W
R
0x0038 CPMUINT
W
R
0x0039 CPMUCLKS
W
R
0x003A CPMUPLL
W
R
0x003B CPMURTI
W
R
0x003C CPMUCOP
W
0x003D
RESERVED
CPMUTEST0
R
W
0x003E
RESERVED
CPMUTEST1
R
W
0x003F
CPMU
ARMCOP
R
W
0x02F0
CPMU
HTCTL
R
W
0x02F1
CPMU
LVCTL
R
W
0x02F2
CPMU
APICTL
R
W
R
0x02F3 CPMUAPITR
W
R
0x02F4 CPMUAPIRH
W
Bit 7
6
5
4
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
0
RTIF
RTIE
PORF
0
PLLSEL
0
PSTP
0
LVRF
0
0
LOCKIF
LOCKIE
0
FM1
FM0
RTDEC
WCOP
0
RTR6
RTR5
RTR4
0
0
RSBCK
WRTMASK
0
0
0
0
0
0
0
0
Bit 7
0
0
0
Bit 6
0
0
0
Bit 5
VSEL
0
0
Bit 4
0
0
0
APICLK
0
APIES
APITR5 APITR4 APITR3 APITR2
APIR15 APIR14 APIR13 APIR12
= Unimplemented or Reserved
3
2
1
SYNDIV[5:0]
REFDIV[3:0]
POSTDIV[4:0]
LOCK
ILAF
OSCIF
0
0
OSCIE
PRE
0
PCE
0
RTI
OSCSEL
0
RTR3
0
0
RTR2
CR2
0
RTR1
CR1
0
0
0
0
0
Bit 3
HTE
0
0
Bit 2
HTDS
LVDS
0
Bit 1
HTIE
LVIE
APIEA APIFE
APITR1 APITR0
APIE
0
APIR11 APIR10 APIR9
Figure 7-3. CPMU Register Summary
Bit 0
UPOSC
0
COP
OSCSEL
0
RTR0
CR0
0
0
0
Bit 0
HTIF
LVIF
APIF
0
APIR8
S12P-Family Reference Manual, Rev. 1.12
204
Freescale Semiconductor