MC9S12P128 Datasheet, PDF (65/564 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

2.3.7 PIM Reserved Register
Address 0x0004 to 0x0007
7
6
5
4
3
R
0
0
0
0
0
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
1. Read: Always reads 0x00
Write: Unimplemented
Figure 2-5. PIM Reserved Register
Port Integration Module (S12PPIMV1)
Access: User read⁽¹⁾
2
1
0
0
0
0
0
0
0
2.3.8 Port E Data Register (PORTE)
Address 0x0008
Access: User read/write⁽¹⁾
7
R
PE7
W
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
Altern.
Function ^ECLKX2
—
—
ECLK
—
—
IRQ
XIRQ
Reset
0
0
0
0
0
0
—⁽²⁾
—²
= Unimplemented or Reserved
Figure 2-6. Port E Data Register (PORTE)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
Table 2-8. PORTE Register Field Descriptions
Field
7
PE
Description
Port E general purpose input/output data—Data Register, ECLKX2 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
6-5, 3-2
PE
Port E general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
65